Ritesh P. Turakhia

According to our database, Ritesh P. Turakhia authored at least 6 papers between 2004 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2009

Bridging DFM Analysis and Volume Diagnostics for Yield Learning - A Case Study.

Ritesh P. Turakhia, Mark Ward, Sandeep Kumar Goel, Brady Benware

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Effective and Efficient Test Pattern Generation for Small Delay Defect.

Sandeep Kumar Goel, Narendra Devta-Prasanna, Ritesh P. Turakhia

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

2007

Silicon evaluation of longest path avoidance testing for small delay defects.

Ritesh P. Turakhia, W. Robert Daasch, Mark Ward, John Van Slyke

Proceedings of the 2007 IEEE International Test Conference, 2007

2006

Changing Test and Data Modeling Requirements for Screening Latent Defects as Statistical Outliers.

Ritesh P. Turakhia, W. Robert Daasch, Joel Lurkins, Brady Benware

IEEE Des. Test Comput., 2006

2005

Defect Screening Using Independent Component Analysis on I_DDQ.

Ritesh P. Turakhia, Brady Benware, Robert Madge, Thaddeus T. Shannon, W. Robert Daasch

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

2004

In Search of the Optimum Test Set - Adaptive Test Methods for Maximum Defect Coverage and Lowest Test Cost.

Robert Madge, Brady Benware, Ritesh P. Turakhia, W. Robert Daasch, Chris Schuermyer, Jens Ruffler

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004