Ahmad A. Al-Yamani

According to our database1, Ahmad A. Al-Yamani authored at least 29 papers between 2000 and 2010.

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Bibliography

2010
Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns.
J. Electron. Test., 2010

2009
Reconfigurable broadcast scan compression using relaxation-based test vector decomposition.
IET Comput. Digit. Tech., 2009

Increasing memory yield in future technologies through innovative design.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008
Comparative study of centralised and distributed compatibility-based test data compression.
IET Comput. Digit. Tech., 2008

2007
A Defect Tolerance Scheme for Nanotechnology Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Energy-delay efficient test.
IET Comput. Digit. Tech., 2007

High defect tolerant low cost memory chips.
Proceedings of the 2007 IEEE International SOC Conference, 2007

Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decompos.
Proceedings of the 16th Asian Test Symposium, 2007

Systematic Scan Reconfiguration.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
DFT for controlled-impedance I/O buffers.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Test chip experimental results on high-level structural test.
ACM Trans. Design Autom. Electr. Syst., 2005

Optimized reseeding by seed ordering and encoding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Effective TARO Pattern Generation.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Segmented Addressable Scan Architecture.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

BIST-Guided ATPG.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Should Illinois-Scan Based Architectures be Centralized or Distributed?
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004
ELF-Murphy Data on Defects and Test Sets.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Test quality for high level structural test.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

2003
Bist Reseeding with very few Seeds.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Built-In Reseeding for Serial Bist.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Parallel Tabu Search in a Heterogeneous Environment.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Seed encoding with LFSRs and cellular automata.
Proceedings of the 40th Design Automation Conference, 2003

2002
Parallelizing Tabu Search on a Cluster of Heterogeneous Workstations.
J. Heuristics, 2002

Testing Digital Circuits with Constraints.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

HPTS: heterogeneous parallel tabu search for VLSI placement.
Proceedings of the 2002 Congress on Evolutionary Computation, 2002

2001
Performance Evaluation of Checksum-Based ABFT.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
A parallel tabu search algorithm for VLSI standard-cell placement.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000


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