Naser MohammadZadeh

Orcid: 0000-0002-7682-3455

According to our database1, Naser MohammadZadeh authored at least 28 papers between 2007 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
AMPS: An Automated Mesochronous Pipeline Scheduler and Design Space Explorer for High Performance Digital Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Exact Mapping of Quantum Circuit Partitions to Building Blocks of the SAQIP Architecture.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

2021
Efficient One-pass Synthesis for Digital Microfluidic Biochips.
ACM Trans. Design Autom. Electr. Syst., 2021

A congestion-aware mixed integer linear programming model for placement and scheduling of quantum circuits with a two-level heuristic solution approach.
Quantum Eng., 2021

Exact Physical Design of Quantum Circuits for Ion-Trap-based Quantum Architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2019
SAQIP: A Scalable Architecture for Quantum Information Processors.
ACM Trans. Archit. Code Optim., 2019

Qubit mapping of one-way quantum computation patterns onto 2D nearest-neighbor architectures.
Quantum Inf. Process., 2019

Anomaly Detection Using SVM as Classifier and Decision Tree for Optimizing Feature Vectors.
ISC Int. J. Inf. Secur., 2019

IoT-Based Anonymous Authentication Protocol Using Biometrics in Smart Homes.
Proceedings of the 16th International ISC (Iranian Society of Cryptology) Conference on Information Security and Cryptology, 2019

2018
A power-performance tunable logic with adjustable threshold pseudo-dynamic building blocks and CMOS compatibility.
Int. J. Circuit Theory Appl., 2018

2017
Quantum circuit physical design flow for 2D nearest-neighbor architectures.
Int. J. Circuit Theory Appl., 2017

2016
Physical synthesis of quantum circuits using templates.
Quantum Inf. Process., 2016

Physical design of quantum circuits in ion trap technology - A survey.
Microelectron. J., 2016

Quantum circuit physical design flow for the multiplexed trap architecture.
Microprocess. Microsystems, 2016

A Game Theory Approach for Malicious Node Detection in MANETs.
J. Inf. Sci. Eng., 2016

LDPC decoder implementation using FPGA.
Proceedings of the 8th International Symposium on Telecommunications, 2016

Lightweight, anonymous and mutual authentication in IoT infrastructure.
Proceedings of the 8th International Symposium on Telecommunications, 2016

2015
An MINLP Model for Scheduling and Placement of Quantum Circuits with a Heuristic Solution Approach.
ACM J. Emerg. Technol. Comput. Syst., 2015

2014
Quantum circuit physical design methodology with emphasis on physical synthesis.
Quantum Inf. Process., 2014

2011
Auxiliary qubit selection: a physical synthesis technique for quantum circuits.
Quantum Inf. Process., 2011

2010
Quantum physical synthesis: Improving physical design by netlist modifications.
Microelectron. J., 2010

2009
Improving Latency of Quantum Circuits by Gate Exchanging.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
The ODYSSEY approach to early simulation-based equivalence checking at ESL level using automatically generated executable transaction-level model.
Microprocess. Microsystems, 2008

A Framework for Object-Oriented Embedded System Development Based on OO-ASIPs.
J. Circuits Syst. Comput., 2008

Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
Using on-chip networks to implement polymorphism in the co-design of object-oriented embedded systems.
J. Comput. Syst. Sci., 2007

Implementation of a jpeg object-oriented ASIP: a case study on a system-level design methodology.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007


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