Ne Kyaw Zwa Lwin
Orcid: 0000-0001-7506-0380Affiliations:
- Nanyang Technological University, Singapore
According to our database1,
Ne Kyaw Zwa Lwin
authored at least 24 papers
between 2014 and 2022.
Collaborative distances:
Collaborative distances:
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Bibliography
2022
An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
High Throughput and Secure Authentication-Encryption on Asynchronous Multicore Processor for Edge Computing IoT Applications.
Proceedings of the International SoC Design Conference, 2020
A Highly Efficient Power Model for Correlation Power Analysis (CPA) of Pipelined Advanced Encryption Standard (AES).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Radiation-Hardened-by-Design (RHBD) Digital Design Approaches: A Case Study on an 8051 Microcontroller.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
2019
A High Throughput and Secure Authentication-Encryption AES-CCM Algorithm on Asynchronous Multicore Processor.
IEEE Trans. Inf. Forensics Secur., 2019
Reconfigurable Routing Paths As Noise Generators Using NoC Platform for Hardware Security Applications.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019
2018
Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
2016
Security analysis of asynchronous-logic QDI cell approach for differential power analysis attack.
Proceedings of the International Symposium on Integrated Circuits, 2016
Experimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC).
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
Radiation-hardened library cell template and its total ionizing dose (TID) delay characterization in 65nm CMOS process.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014