Joseph Sylvester Chang
Orcid: 0000-0003-0991-8339
According to our database1,
Joseph Sylvester Chang
authored at least 129 papers
between 1998 and 2022.
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Bibliography
2022
A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks.
IEEE Trans. Very Large Scale Integr. Syst., 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 12-W 96.1%-Efficiency eFuse-Based Ultrafast Battery Charger Supporting Wireless and USB Power Inputs.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
A Low-Profile High-Efficiency Fast Battery Charger With Unifiable Constant-Current and Constant-Voltage Regulation.
IEEE Trans. Circuits Syst., 2020
A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Radiation-Hardened-by-Design (RHBD) Digital Design Approaches: A Case Study on an 8051 Microcontroller.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A Fully Additive Low-Temperature All-Air Low-Variation Printed/Flexible Electronics With Self-Compensation for Bending: Codesign From Materials, Design, Fabrication, and Applications.
Proc. IEEE, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A 30V 2A Real-Time Programmable Solid-State Circuit Breaker with Improved Detection-Speed and Enhanced Power-Efficiency.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
A Monolithic I<sup>2</sup>V<sup>2</sup>-Controlled Dual-Phase LED Matrix Driver for Automotive Adaptive Driving Beam (ADB) Headlighting.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019
2018
A Calibration-Free/DEM-Free 8-bit 2.4-GS/s Single-Core Digital-to-Analog Converter With a Distributed Biasing Scheme.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design.
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 65-nm CMOS Low Dropout Regulator Featuring >60-dB PSRR Over 10-MHz Frequency Range and 100-mA Load Current Range.
IEEE J. Solid State Circuits, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Power-Loss and Design Space Analyses for Fully-Integrated Switched-Mode DC-DC Converters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
An Air-Core Coupled-Inductor Based Dual-Phase Output Stage for Point-of-Load Converters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
Radiation Hardening By Design Integrated Circuits Enabling Low-Cost Satellites for Internet-of-Things.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
2017
A 400-MS/s 10-b 2-b/Step SAR ADC With 52-dB SNDR and 5.61-mW Power Dissipation in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A 10-GS/s 4-Bit Single-Core Digital-to-Analog Converter for Cognitive Ultrawidebands.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
A 5.6 ppm/°C Temperature Coefficient, 87-dB PSRR, Sub-1-V Voltage Reference in 65-nm CMOS Exploiting the Zero-Temperature-Coefficient Point.
IEEE J. Solid State Circuits, 2017
A Circuits and Systems Perspective of Organic/Printed Electronics: Review, Challenges, and Contemporary and Emerging Design Approaches.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017
A low-harmonics low-noise randomized modulation scheme for multi-phase DC-DC converters.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
A novel high-rate hybrid window ADC design for monolithic digitally-controlled DC-DC converters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
A class-E RF power amplifier with a novel matching network for high-efficiency dynamic load modulation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Review: A fully-additive printed electronics process with very-low process variations (Bent and unbent substrates) and PDK.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
Proceedings of the International Symposium on Integrated Circuits, 2016
A high-efficiency Class-E polar power-amplifier with a novel digitally-controlled output matching network.
Proceedings of the International Symposium on Integrated Circuits, 2016
Proceedings of the International Symposium on Integrated Circuits, 2016
Proceedings of the International Symposium on Integrated Circuits, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Experimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applications.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
IEEE Trans. Circuits Syst. II Express Briefs, 2015
Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer.
IET Circuits Devices Syst., 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A novel subthreshold voltage reference featuring 17ppm/°C TC within -40°C to 125°C and 75dB PSRR.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC).
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
2014
A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
A 101 dB PSRR, 0.0027% THD + N and 94% Power-Efficiency Filterless Class D Amplifier.
IEEE J. Solid State Circuits, 2014
An investigation into the effect of carrier generators on power supply noise in PWM Class D amplifiers.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Fully-Additive printed electronics on flexible substrates: A Fully-Additive RFID tag.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Radiation-hardened library cell template and its total ionizing dose (TID) delay characterization in 65nm CMOS process.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive V<sub>DD</sub> System for Wireless Sensor Networks.
IEEE J. Solid State Circuits, 2013
Synchronous-Logic and Asynchronous-Logic 8051 Microcontroller Cores for Realizing the Internet of Things: A Comparative Study on Dynamic Voltage Scaling and Variation Effects.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2013
Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A 250mV sub-threshold asynchronous 8051microcontroller with a novel 16T SRAM cell for improved reliability in 40nm CMOS.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
2012
Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors.
IEEE J. Solid State Circuits, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the International Symposium on Electronic System Design, 2012
Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Microprocess. Microsystems, 2011
Improved asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic with high speed and low power operation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
IET Circuits Devices Syst., 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
A Low-Voltage Micropower Asynchronous Multiplier With Shift-Add Multiplication Approach.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
A Low THD Analog Class D Amplifier based on Self-oscillating Modulation with Complete Feedback Network.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Fine-grained Power Gating for Leakage and Short-circuit Power Reduction by using Asynchronous-logic.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
IEEE J. Solid State Circuits, 2007
IET Comput. Digit. Tech., 2007
IET Circuits Devices Syst., 2007
Design of several asynchronous-logic macrocells for a low-voltage micropower cell library.
IET Circuits Devices Syst., 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Fourier series analysis of the nonlinearities in analog closed-loop PWM class D amplifiers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Fourier Series Analysis for Nonlinearities Due to the Power Supply Noise in Open-Loop Class D Amplifiers.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Proceedings of the 5th Annual IEEE/ACIS International Conference on Computer and Information Science (ICIS 2006) and 1st IEEE/ACIS International Workshop on Component-Based Software Engineering, 2006
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
A micropower low-distortion digital class-D amplifier based on an algorithmic pulsewidth modulator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Modeling external feedback path of an ITE digital hearing instrument for acoustic feedback cancellation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A combined interpolatorless interpolation and high accuracy sampling process for digital class D amplifiers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
A low power 16-bit Booth Leapfrog array multiplier using Dynamic Adders.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A novel combined first and second order Lagrange interpolation sampling process for a digital class D amplifier.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2003
A Low Voltage Micropower 16-Word by 16-Bit 3-Port Asynchronous Register File.
Proceedings of the International Conference on VLSI, 2003
A novel sampling process and pulse generator for a low distortion digital pulse-width modulator for digital class D amplifiers.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
A Hybrid Genetic Hill-climbing Algorithm for Four-Coloring Map Problems.
Proceedings of the Design and Application of Hybrid Intelligent Systems, 2003
2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
2001
A novel low-voltage low-power wave digital filter bank for an intelligent noise reduction digital hearing instrument.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
A digital Class D amplifier design embodying a novel sampling process and pulse generator.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
A novel low-power low-voltage Class D amplifier with feedback for improving THD, power efficiency and gain linearity.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000
An investigation on the parameters affecting total harmonic distortion in class D amplifiers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
A novel self-tuning pulse width modulator based on master-slave architecture for a Class D amplifier.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
A process-independent threshold voltage inverter-comparator for pulse width modulation applications.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
1998
IEEE Trans. Speech Audio Process., 1998