Kwen-Siong Chong
Orcid: 0000-0003-1512-2003
According to our database1,
Kwen-Siong Chong
authored at least 75 papers
between 2002 and 2023.
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Bibliography
2023
Improving FPGA-based Async-logic AES Accelerator with the Integration of Sync-logic Block RAMs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks.
IEEE Trans. Very Large Scale Integr. Syst., 2022
A High-Accuracy and Energy-Efficient CORDIC Based Izhikevich Neuron With Error Suppression and Compensation.
IEEE Trans. Biomed. Circuits Syst., 2022
Design and Analysis of Area and Energy Efficient Reconfigurable Cryptographic Accelerator for Securing IoT Devices.
Sensors, 2022
An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2022
2021
A Novel Normalized Variance-Based Differential Power Analysis Against Masking Countermeasures.
IEEE Trans. Inf. Forensics Secur., 2021
A Power-Aware Toggling-Frequency Actuator in Data-Toggling SRAM for Secure Data Protection.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
An Energy-Efficient Deep Belief Network Processor Based on Heterogeneous Multi-Core Architecture With Transposable Memory and On-Chip Learning.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
Proceedings of the 19th IEEE International New Circuits and Systems Conference, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
High Throughput and Secure Authentication-Encryption on Asynchronous Multicore Processor for Edge Computing IoT Applications.
Proceedings of the International SoC Design Conference, 2020
A Highly Efficient Power Model for Correlation Power Analysis (CPA) of Pipelined Advanced Encryption Standard (AES).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Radiation-Hardened-by-Design (RHBD) Digital Design Approaches: A Case Study on an 8051 Microcontroller.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
An Energy-efficient Multi-core Restricted Boltzmann Machine Processor with On-chip Bio-plausible Learning and Reconfigurable Sparsity.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
2019
A High Throughput and Secure Authentication-Encryption AES-CCM Algorithm on Asynchronous Multicore Processor.
IEEE Trans. Inf. Forensics Secur., 2019
A Highly Efficient Side Channel Attack with Profiling through Relevance-Learning on Physical Leakage Information.
IEEE Trans. Dependable Secur. Comput., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Reconfigurable Routing Paths As Noise Generators Using NoC Platform for Hardware Security Applications.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019
2018
Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Radiation Hardening By Design Integrated Circuits Enabling Low-Cost Satellites for Internet-of-Things.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
A Comparative Analysis of 65nm CMOS SRAM and Commercial SRAMs in Security Vulnerability Evaluation.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
2017
Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Highly secured state-shift local clock circuit to countermeasure against side channel attack.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
DPA-resistant QDI dual-rail AES S-Box based on power-balanced weak-conditioned half-buffer.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
Secured Low Power Overhead Compensator Look-Up-Table (LUT) Substitution Box (S-Box) Architecture.
Proceedings of the IEEE International Conference on Networking, 2016
Proceedings of the International Symposium on Integrated Circuits, 2016
Security analysis of asynchronous-logic QDI cell approach for differential power analysis attack.
Proceedings of the International Symposium on Integrated Circuits, 2016
Experimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applications.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
Interceptive side channel attack on AES-128 wireless communications for IoT applications.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer.
IET Circuits Devices Syst., 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC).
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA).
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Circuits Syst. Signal Process., 2014
Radiation-hardened library cell template and its total ionizing dose (TID) delay characterization in 65nm CMOS process.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive V<sub>DD</sub> System for Wireless Sensor Networks.
IEEE J. Solid State Circuits, 2013
Synchronous-Logic and Asynchronous-Logic 8051 Microcontroller Cores for Realizing the Internet of Things: A Comparative Study on Dynamic Voltage Scaling and Variation Effects.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2013
Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A 250mV sub-threshold asynchronous 8051microcontroller with a novel 16T SRAM cell for improved reliability in 40nm CMOS.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
2012
Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors.
IEEE J. Solid State Circuits, 2012
Proceedings of the International Symposium on Electronic System Design, 2012
Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Improved asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic with high speed and low power operation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2009
A Low-Voltage Micropower Asynchronous Multiplier With Shift-Add Multiplication Approach.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Fine-grained Power Gating for Leakage and Short-circuit Power Reduction by using Asynchronous-logic.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2007
IEEE J. Solid State Circuits, 2007
IET Circuits Devices Syst., 2007
Design of several asynchronous-logic macrocells for a low-voltage micropower cell library.
IET Circuits Devices Syst., 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
A low power 16-bit Booth Leapfrog array multiplier using Dynamic Adders.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002