Tong Lin
Orcid: 0000-0002-8112-0439Affiliations:
- Nanyang Technological University of Singapore, School of Electrical and Electronic Engineering, Singapore
According to our database1,
Tong Lin
authored at least 24 papers
between 2009 and 2024.
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Bibliography
2024
Integrated Circuit Mask-Generative Adversarial Network for Circuit Annotation With Targeted Data Augmentation.
IEEE Intell. Syst., 2024
2023
GraphClusNet: A Hierarchical Graph Neural Network for Recovered Circuit Netlist Partitioning.
IEEE Trans. Artif. Intell., October, 2023
Patch-Based Adversarial Training for Error-Aware Circuit Annotation of Delayered IC Images.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2023
SEM2GDS: A Deep-Learning Based Framework To Detect Malicious Modifications In IC Layout.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the 49th Annual Conference of the IEEE Industrial Electronics Society, 2023
2022
Delayered IC image analysis with template-based Tanimoto Convolution and Morphological Decision.
IET Circuits Devices Syst., 2022
Unsupervised Domain Adaptation with Histogram-gated Image Translation for Delayered IC Image Analysis.
CoRR, 2022
2021
Joint Anomaly Detection and Inpainting for Microscopy Images Via Deep Self-Supervised Learning.
Proceedings of the 2021 IEEE International Conference on Image Processing, 2021
2019
IEEE Intell. Syst., 2019
Global Template Projection and Matching Method for Training-Free Analysis of Delayered IC Images.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
Hybrid K-Means Clustering and Support Vector Machine Method for via and Metal Line Detections in Delayered IC Images.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018
2017
Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template.
IEEE Trans. Very Large Scale Integr. Syst., 2017
2016
Experimental investigation into radiation-hardening-by-design (RHBD) flip-flop designs in a 65nm CMOS process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
Fully-Additive printed electronics on flexible substrates: A Fully-Additive RFID tag.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Radiation-hardened library cell template and its total ionizing dose (TID) delay characterization in 65nm CMOS process.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
2013
An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive V<sub>DD</sub> System for Wireless Sensor Networks.
IEEE J. Solid State Circuits, 2013
A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2009
Fine-grained Power Gating for Leakage and Short-circuit Power Reduction by using Asynchronous-logic.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009