Ioannis Voyiatzis

Proceedings of the PCI 2020: 24th Pan-Hellenic Conference on Informatics, 2020

Autonomous drone charging stations: A survey.

[BibT_eX]

[DOI]

Proceedings of the PCI 2020: 24th Pan-Hellenic Conference on Informatics, 2020

A Review on Hardware Security Countermeasures for IoT: Emerging Mechanisms and Machine Learning Solutions.

[BibT_eX]

[DOI]

Emmanouel T. Michailidis

Dimitrios G. Kogias

Proceedings of the PCI 2020: 24th Pan-Hellenic Conference on Informatics, 2020

2018

A low-cost smart home for the assistance of elderly persons and patients.

[BibT_eX]

[DOI]

Proceedings of the 22nd Pan-Hellenic Conference on Informatics, 2018

Programmable logic for single-output functions.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

SIC pair generation in near-optimal time with carry-look ahead adders.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

2017

SIC pair generation in optimal time using rotatable counters.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE European Test Symposium, 2017

Standards-based tools and services for building lifelong learning pathways.

[BibT_eX]

[DOI]

Anastasios Koutoumanos

Giuseppe Airo Farulla

Peeter Ellervee

Carlos Delgado Kloos

Raquel M. Crespo García

Proceedings of the 2017 IEEE Global Engineering Education Conference, 2017

Processor-based Symmetric Transparent BIST.

[BibT_eX]

[DOI]

Giuseppe Airo Farulla

Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

On the generation of binary functions with low-overhead.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

2016

Software-based SIC pair Generation.

[BibT_eX]

[DOI]

Kiriakos Patriarcheas

Proceedings of the 20th Pan-Hellenic Conference on Informatics, 2016

Low Cost Boolean Function generation.

[BibT_eX]

[DOI]

Proceedings of the 20th Pan-Hellenic Conference on Informatics, 2016

2015

On the Generation of SIC Pairs in Optimal Time.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

Accumulator-based generation for serial TPG.

[BibT_eX]

[DOI]

Proceedings of the 19th Panhellenic Conference on Informatics, 2015

On the use of hard faults to generate test sets.

[BibT_eX]

[DOI]

Proceedings of the 19th Panhellenic Conference on Informatics, 2015

Modulo 2n ± 1 Fused Add-Multiply Units.

[BibT_eX]

[DOI]

Kostas Tsoumanis

Kiamal Z. Pekmestzi

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Symmetric transparent on-line BIST of word-organized memories with binary adders.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE European Test Symposium, 2015

Detecting untestable hardware Trojan with non-intrusive concurrent on line testing.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

A concurrent BIST scheme for read only memories.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Test set embedding into hardware generated sequences using an embedding algorithm.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

2014

Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Aliasing Reduction in Accumulator-Based Response Verification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Stealth Assessment of Hardware Trojans in simple Processors.

[BibT_eX]

[DOI]

Proceedings of the 18th Panhellenic Conference on Informatics, 2014

Concurrent online BIST for sequential circuits exploiting input reduction and output space compaction.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE European Test Symposium, 2014

Accumulator-based test-per-clock scheme for low-power on-chip application of test patterns.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE European Test Symposium, 2014

DTIS 2014 foreword.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Low overhead output response compaction in RAS architectures.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Accumulator-based self-adjusting output data compression for embedded word-organized DRAMs.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

On the design of efficient modulo 2<sup>n</sup>+1 multiply-add-add units.

[BibT_eX]

[DOI]

Kostas Tsoumanis

Kiamal Z. Pekmestzi

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

2013

Joint special Issue from best papers of DTIS'10 and DTIS'11.

[BibT_eX]

[DOI]

Serge Bernard

Mohamed Masmoudi

Microelectron. J., 2013

An effective two-pattern test generator for Arithmetic BIST.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2013

On the design of modulo 2<sup>n</sup> + 1 dot product and generalized multiply-add units.

[BibT_eX]

[DOI]

Nikolaos Moschopoulos

Kiamal Z. Pekmestzi

Comput. Electr. Eng., 2013

A low-cost input vector monitoring concurrent BIST scheme.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Test set embedding into accumulator-generated sequences targeting hard-to-detect faults.

[BibT_eX]

[DOI]

Stelios Neophytou

Maria K. Michael

Stavros Hadjitheophanous

Proceedings of the 8th International Design and Test Symposium, 2013

Transparent testing for intra-word memory faults.

[BibT_eX]

[DOI]

Proceedings of the 8th International Design and Test Symposium, 2013

Embedding test vectors in accumulator - based TPG using progressive search.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

Symmetric transparent online BIST for arrays of word-organized RAMs.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

2012

Accumulator Based 3-Weight Pattern Generation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Arithmetic module-based built-in self test architecture for two-pattern testing.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2012

Test Set Embedding into Low-Power BIST Sequences Using Maximum Bipartite Matching.

[BibT_eX]

[DOI]

Kyriakos Axiotis

Nikolaos S. Papaspyrou

Hera Antonopoulou

Proceedings of the 16th Panhellenic Conference on Informatics, PCI 2012, 2012

Design and Implementation of an E-exam System Based on the Android Platform.

[BibT_eX]

[DOI]

Proceedings of the 16th Panhellenic Conference on Informatics, PCI 2012, 2012

A novel architecture to reduce test time in march-based SRAM tests.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2012

Test vector embedding in accumulators with stored carry in O(1) time.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2012

Test set embedding into low-power sequences based on a traveling salesman problem formulation.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2012

ALU based address generation for RAMs.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2012

Input vector monitoring on line concurrent BIST based on multilevel decoding logic.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

An Accumulator - Based Test-Per-Clock Scheme.

[BibT_eX]

[DOI]

Dimitris Magos

Steffen Tarnick

IEEE Trans. Very Large Scale Integr. Syst., 2011

A Novel SRAM-Cell Based Input Vector Monitoring Concurrent BIST Architecture.

[BibT_eX]

[DOI]

Hera Antonopoulou

Proceedings of the 16th European Test Symposium, 2011

2010

Recursive Pseudo-Exhaustive Two-Pattern Generation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

An efficient architecture for accumulator-based test generation of SIC pairs.

[BibT_eX]

[DOI]

Microelectron. J., 2010

On Embedding Test Sets into Hardware Generated Sequences.

[BibT_eX]

[DOI]

Proceedings of the 14th Panhellenic Conference on Informatics, 2010

2009

Embedding Test Patterns in Accumulator-Generated Sequences in O(1) Time.

[BibT_eX]

[DOI]

Nestor Ioannidis

Proceedings of the PCI 2009, 2009

An Input Vector Monitoring Concurrent BIST scheme exploiting .

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

2008

A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences.

[BibT_eX]

[DOI]

VLSI Design, 2008

An Accumulator-Based Compaction Scheme For Online BIST of RAMs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

An Input Vector Monitoring Concurrent BIST Architecture Based on a Precomputed Test Set.

[BibT_eX]

[DOI]

Miltiadis Hatzimihail

IEEE Trans. Computers, 2008

An ALU-Based BIST Scheme for Word-Organized RAMs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2008

On Embedding Test Patterns into Low-Power Bist Sequences.

[BibT_eX]

[DOI]

J. Comput. Inf. Syst., 2008

A Low-Cost Accumulator-Based Test Pattern Generation Architecture.

[BibT_eX]

[DOI]

Dimitris Magos

Steffen Tarnick

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

2007

Accumulator-based pseudo-exhaustive two-pattern generation.

[BibT_eX]

[DOI]

J. Syst. Archit., 2007

Reliability considerations in mobile devices.

[BibT_eX]

[DOI]

Hera Antonopoulou

S. Sinitos

Proceedings of the 3rd International Conference on Mobile Multimedia Communications, 2007

2006

A SiC Pair Generator for a Bilbo Environment.

[BibT_eX]

[DOI]

Dimitris Kehagias

J. Circuits Syst. Comput., 2006

2005

Accumulator-based test generation for robust sequential fault testing in DSP cores in near-optimal time.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

A concurrent built-in self-test architecture based on a self-testing RAM.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2005

A Low-Cost Concurrent BIST Scheme for Increased Dependability.

[BibT_eX]

[DOI]

Constantin Halatsis

IEEE Trans. Dependable Secur. Comput., 2005

Test Vector Embedding into Accumulator-Generated Sequences: A Linear-Time Solution.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2005

A concurrent BIST scheme for on-line/off-line testing based on a pre-computed test set.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Accumulator-Based Weighted Pattern Generation.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

2004

A counter-based pseudo-exhaustive pattern generator for BIST applications.

[BibT_eX]

[DOI]

Microelectron. J., 2004

1999

An Accumulator-Based BIST Approach for Two-Pattern Testing.

[BibT_eX]

[DOI]

J. Electron. Test., 1999

1998

R-CBIST: an effective RAM-based input vector monitoring concurrent BIST technique.

[BibT_eX]

[DOI]

Dimitris Nikolos

Constantinos Halatsis

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997

Αρχιτεκτονικές ενσωματωμένης αυτοδοκιμής για ψηφιακά κυκλώματα σε τεχνολογία CMOS VLSI

[BibT_eX]

[DOI]

PhD thesis, 1997

1996

An efficient built-in self test method for robust path delay fault testing.

[BibT_eX]

[DOI]

J. Electron. Test., 1996

1995

Accumulator-based BIST approach for stuck-open and delay fault testing.

[BibT_eX]

[DOI]

Proceedings of the 1995 European Design and Test Conference, 1995

An efficient comparative concurrent Built-In Self-Test technique.

[BibT_eX]

[DOI]

Dimitris Nikolos