Noriyuki Ito

According to our database1, Noriyuki Ito authored at least 8 papers between 1990 and 2009.

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Timeline

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Bibliography

2009
Efficient Power Network Analysis Considering Multidomain Clock Gating.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

2007
Fast power network analysis with multiple clock domains.
Proceedings of the 25th International Conference on Computer Design, 2007

Design Methodology for 2.4GHz Dual-Core Microprocessor.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Diagonal routing in high performance microprocessor design.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Delay defect screening for a 2.16GHz SPARC64 microprocessor.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2004
Detection of multiple transitions in delay fault test of SPARC64 microprocessor.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003
A Physical Design Methodology for 1.3GHz SPARC64 Microprocessor.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

1990
Automatic Incorporation of On-Chip Testability Circuits.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990


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