Olga Golubeva

Orcid: 0000-0003-0167-7729

According to our database1, Olga Golubeva authored at least 13 papers between 2001 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2025
Generative Design of Urban Identity.
Proceedings of the Novel and Intelligent Digital Systems: Proceedings of the 5th International Conference, 2025

2024
Generative Design of Urban Facilities Using Knowledge Models of Building Codes.
Proceedings of the Novel and Intelligent Digital Systems: Proceedings of the 4th International Conference, 2024

2010
Architectural Leakage Power Minimization of Scratchpad Memories by Application-Driven Subbanking.
IEEE Trans. Computers, 2010

2007
Locality-driven architectural cache sub-banking for leakage energy reduction.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

On the energy efficiency of synchronization primitives for shared-memory single-chip multiprocessors.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Architectural leakage-aware management of partitioned scratchpad memories.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Software-Implemented Hardware Fault Tolerance.
Springer, ISBN: 978-0-387-26060-0, 2006

2004
Automatic Generation of Validation Stimuli for Application-Specific Processors.
Proceedings of the 2004 Design, 2004

2003
An RT-level Concurrent Error Detection Technique for Data Dominated Systems.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

High-level test generation for hardware testing and software validation.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

Soft-Error Detection Using Control Flow Assertions.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002
High-level and hierarchical test sequence generation.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

2001
Totally Self-Checking FSM Design Based on Multilevel Synthesis Methods and FPGA Implemetation.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001


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