Mirko Loghi

Proceedings of the ICONS 2022: International Conference on Neuromorphic Systems, Knoxville, TN, USA, July 27, 2022

2021

Ferroelectric based FETs and synaptic devices for highly energy efficient computational technologies.

[BibT_eX]

[DOI]

CoRR, 2021

Modelling and design of FTJs as high reading-impedance synaptic devices.

[BibT_eX]

[DOI]

CoRR, 2021

2018

A Portable 3-D Imaging FMCW MIMO Radar Demonstrator With a $24\times 24$ Antenna Array for Medium-Range Applications.

[BibT_eX]

[DOI]

Alexander Rudolf Ganis

Enric Miralles Navarro

Bernhard Schoenlinner

IEEE Trans. Geosci. Remote. Sens., 2018

2014

Energy/Lifetime Cooptimization by Cache Partitioning With Graceful Performance Degradation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Dynamic Indexing: Leakage-Aging Co-Optimization for Caches.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013

Firefly-Inspired Synchronization of Sensor Networks with Variable Period Lengths.

[BibT_eX]

[DOI]

Stefan Wieser

Pier Luca Montessoro

Proceedings of the Adaptive and Natural Computing Algorithms, 2013

2012

Aging-aware caches with graceful degradation of performance.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Energy-optimal caches with guaranteed lifetime.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Application-specific memory partitioning for joint energy and lifetime optimization.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Buffering of frequent accesses for reduced cache aging.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Partitioned cache architectures for reduced NBTI-induced aging.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Architectural Leakage Power Minimization of Scratchpad Memories by Application-Driven Subbanking.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2010

Dynamic indexing: concurrent leakage and aging optimization for caches.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Aging effects of leakage optimizations for caches.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009

Tag Overflow Buffering: Reducing Total Memory Energy by Reduced-Tag Matching.

[BibT_eX]

[DOI]

Paolo Azzoni

IEEE Trans. Very Large Scale Integr. Syst., 2009

A cosimulation methodology for HW/SW validation and performance estimation.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

Energy-optimal synchronization primitives for single-chip multi-processors.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2007

Power macromodeling of MPSoC message passing primitives.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2007

Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2007

SystemC co-simulation for core-based embedded systems.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2007

Locality-driven architectural cache sub-banking for leakage energy reduction.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

On the energy efficiency of synchronization primitives for shared-memory single-chip multiprocessors.

[BibT_eX]

[DOI]

Olga Golubeva

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Architectural leakage-aware management of partitioned scratchpad memories.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Cache coherence tradeoffs in shared-memory MPSoCs.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2006

Synchronization-driven dynamic speed scaling for MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

ISS-centric modular HW/SW co-simulation.

[BibT_eX]

[DOI]

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

2005

Dynamic and Formal Verification of Embedded Systems: A Comparative Survey.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2005

Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software Solutions.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Tag Overflow Buffering: An Energy-Efficient Cache Architecture.

[BibT_eX]

[DOI]

Paolo Azzoni

Proceedings of the 2005 Design, 2005

Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

2004

Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Cycle-accurate power analysis for multiprocessor systems-on-a-chip.

[BibT_eX]

[DOI]