Maurizio Rebaudengo

According to our database1, Maurizio Rebaudengo authored at least 146 papers between 1993 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2018
Internet of Things for fall prediction and prevention.
J. Comput. Meth. in Science and Engineering, 2018

A cost-effective proposal for an RFID-based system for agri-food traceability.
IJAHUC, 2018

A fuzzy approach for power savings in both infrastructure and ad hoc WLANs.
Computers in Industry, 2018

Particulate Matter Monitoring in Mixed Indoor/Outdoor Industrial Applications: A Case Study.
Proceedings of the 23rd IEEE International Conference on Emerging Technologies and Factory Automation, 2018

2017
A Key Distribution Scheme for Mobile Wireless Sensor Networks: q-Composite.
IEEE Trans. Information Forensics and Security, 2017

A security protocol for RFID traceability.
Int. J. Communication Systems, 2017

TMR technique for mutex kernel data structures.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Mixed public and secret-key cryptography for wireless sensor networks.
Proceedings of the Tenth International Conference on Mobile Computing and Ubiquitous Network, 2017

Urban dust monitoring from ground level to last floor.
Proceedings of the Tenth International Conference on Mobile Computing and Ubiquitous Network, 2017

Polynomial classification model for real-time fall prediction system.
Proceedings of the 41st IEEE Annual Computer Software and Applications Conference, 2017

DIIG: A Distributed Industrial IoT Gateway.
Proceedings of the 41st IEEE Annual Computer Software and Applications Conference, 2017

2016
Investigation of Interference Models for RFID Systems.
Sensors, 2016

A Mobile and Low-Cost System for Environmental Monitoring: A Case Study.
Sensors, 2016

KITO tool: A fault injection environment in Linux kernel data structures.
Microelectronics Reliability, 2016

Fast Hierarchical Key Management Scheme With Transitory Master Key for Wireless Sensor Networks.
IEEE Internet of Things Journal, 2016

A Neural Network Model Based on Co-occurrence Matrix for Fall Prediction.
Proceedings of the Wireless Mobile Communication and Healthcare, 2016

Kanzi: A Distributed, In-memory Key-Value Store.
Proceedings of the Posters and Demos Session of the 17th International Middleware Conference, 2016

2015
An innovative parallel fuzzy scheme for low-power consumption in IEEE 802.11 devices.
Proceedings of the 13th IEEE International Conference on Industrial Informatics, 2015

A novel simulator for RFID reader-to-reader anti-collision protocols.
Proceedings of the 2015 International EURASIP Workshop on RFID Technology, 2015

Experimental investigation on the interference between UHF RFID and GSM.
Proceedings of the 2015 International EURASIP Workshop on RFID Technology, 2015

2014
Improving Colorwave with the probabilistic approach for reader-to-reader anti-collision TDMA protocols.
Wireless Networks, 2014

Key Management for Static Wireless Sensor Networks With Node Adding.
IEEE Trans. Industrial Informatics, 2014

Performance analysis of reliable flooding in duty-cycle wireless sensor networks.
Trans. Emerging Telecommunications Technologies, 2014

Software-implemented fault injection in operating system kernel mutex data structure.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

A parallel fuzzy scheme to improve power consumption management in Wireless Sensor Networks.
Proceedings of the 2014 IEEE Emerging Technology and Factory Automation, 2014

Fault injection in the process descriptor of a Unix-based operating system.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013
DCNS: An Adaptable High Throughput RFID Reader-to-Reader Anticollision Protocol.
IEEE Trans. Parallel Distrib. Syst., 2013

A Geometric Distribution Reader Anti-Collision Protocol for RFID Dense Reader Environments.
IEEE Trans. Automation Science and Engineering, 2013

Evaluation of single and additive interference models for RFID collisions.
Mathematical and Computer Modelling, 2013

Trade-off between maximum cardinality of collision sets and accuracy of RFID reader-to-reader collision detection.
EURASIP J. Emb. Sys., 2013

Improving Key Negotiation in Transitory Master Key Schemes for Wireless Sensor Networks.
Proceedings of the Sensor Systems and Software - 4th International ICST Conference, 2013

Simulation and Evaluation of the Interference Models for RFID Reader-to-Reader Collisions.
Proceedings of the 11th International Conference on Advances in Mobile Computing & Multimedia, 2013

Hierarchical Key Negotiation Technique for Transitory Master Key Schemes in Wireless Sensor Networks.
Proceedings of the 2013 Eighth International Conference on Broadband and Wireless Computing, 2013

Simulating Reader-to-Reader Interference in RFID Systems.
Proceedings of the 27th International Conference on Advanced Information Networking and Applications Workshops, 2013

2012
A Fair and High Throughput Reader-to-Reader Anticollision Protocol in Dense RFID Networks.
IEEE Trans. Industrial Informatics, 2012

A Comparison between Single and Additive Contribution in RFID Reader-to-Reader Interference Models.
Proceedings of the Sixth International Conference on Innovative Mobile and Internet Services in Ubiquitous Computing, 2012

2011
Probabilistic DCS: An RFID reader-to-reader anti-collision protocol.
J. Network and Computer Applications, 2011

Monitoring and Modeling Building Energy Expenditure with Sensor Networks.
Proceedings of the PECCS 2011, 2011

Adaptive Fuzzy-MAC for Power Reduction in Wireless Sensor Networks.
Proceedings of the 4th IFIP International Conference on New Technologies, 2011

An Adaptive Power-Aware Multi-hop Routing Algorithm for Wireless Sensor Networks.
Proceedings of the Eighth International Conference on Information Technology: New Generations, 2011

Performance evaluation of reliable and unreliable opportunistic flooding in wireless sensor network.
Proceedings of the 17th IEEE International Conference on Networks, 2011

Evaluation Framework of Opportunistic Flooding in Wireless Sensor Networks.
Proceedings of the IEEE/IFIP 9th International Conference on Embedded and Ubiquitous Computing, 2011

2010
Tampering in RFID: A Survey on Risks and Defenses.
MONET, 2010

Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug.
IET Computers & Digital Techniques, 2010

2009
On Improving Automation by Integrating RFID in the Traceability Management of the Agri-Food Sector.
IEEE Trans. Industrial Electronics, 2009

Opportunities and Constraints for Wide Adoption of RFID in Agri-Food.
IJAPUC, 2009

Introducing Probability in RFID Reader-to-Reader Anti-collision.
Proceedings of The Eighth IEEE International Symposium on Networking Computing and Applications, 2009

Random key pre-distribution with transitory master key for wireless sensor networks.
Proceedings of the 5th international student workshop on Emerging networking experiments and technologies, 2009

2007
A System-layer Infrastructure for SoC Diagnosis.
J. Electronic Testing, 2007

Design of an UHF RFID transponder for secure authentication.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Safety Evaluation of NanoFabrics.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Agri-Food Traceability Management using a RFID System with Privacy Protection.
Proceedings of the 21st International Conference on Advanced Information Networking and Applications (AINA 2007), 2007

2006
A New Hybrid Fault Detection Technique for Systems-on-a-Chip.
IEEE Trans. Computers, 2006

A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

On the Automation of the Test Flow of Complex SoCs.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Embedded Memory Diagnosis: An Industrial Workflow.
Proceedings of the 2006 IEEE International Test Conference, 2006

Combined software and hardware techniques for the design of reliable IP processors.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Software-Implemented Hardware Fault Tolerance.
Springer, ISBN: 978-0-387-26060-0, 2006

2005
Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Integrating BIST Techniques for On-Line SoC Testing.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Exploiting an infrastructure IP to reduce memory diagnosis costs in SoCs.
Proceedings of the 10th European Test Symposium, ETS 2005, Tallinn, 2005

On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core.
Proceedings of the 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June, 2005

An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004
A New Approach to Software-Implemented Fault Tolerance.
J. Electronic Testing, 2004

A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.
J. Electronic Testing, 2004

Using Infrastructure IPs to Support SW-Based Self-Test of Processor Cores.
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

Hybrid Soft Error Detection by Means of Infrastructure IP Cores.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Exploiting an I-IP for In-Field SOC Test.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA.
Proceedings of the 2004 Design, 2004

2003
New techniques for efficiently assessing reliability of SOCs.
Microelectronics Journal, 2003

Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor.
J. Electronic Testing, 2003

Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Analyzing SEU Effects in SRAM-based FPGAs.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

An efficient algorithm for the extraction of compressed diagnostic information from embedded memory cores.
Proceedings of 9th IEEE International Conference on Emerging Technologies and Factory Automation, 2003

Soft-Error Detection Using Control Flow Assertions.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor.
Proceedings of the 2003 Design, 2003

A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories.
Proceedings of the 2003 Design, 2003

2002
Initializability analysis of synchronous sequential circuits.
ACM Trans. Design Autom. Electr. Syst., 2002

An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits.
J. Electronic Testing, 2002

A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

Analysis of SEU Effects in a Pipelined Processor.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 2002

A New Functional Fault Model for FPGA Application-Oriented Testing.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001
A Source-to-Source Compiler for Generating Dependable Software.
Proceedings of the 1st IEEE International Workshop on Source Code Analysis and Manipulation (SCAM 2001), 2001

Exploiting FPGA for Accelerating Fault Injection Experiments.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits.
Proceedings of the Field-Programmable Logic and Applications, 2001

Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits .
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

System safety through automatic high-level code transformations: an experimental evaluation.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

FPGA-Based Fault Injection for Microprocessor Systems.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

A P1500 Compliant BIST-Based Approach to Embedded RAM Diagnosis.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
Low Power BIST via Non-Linear Hybrid Cellular Automata.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Speeding-Up Fault Injection Campaigns in VHDL Models.
Proceedings of the Computer Safety, 2000

Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

New Techniques for Accelerating Fault Injection in VHDL Descriptions.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

Behavioral-level test vector generation for system-on-chip designs.
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

Prediction of Power Requirements for High-Speed Circuits.
Proceedings of the Real-World Applications of Evolutionary Computing, 2000

An Experimental Evaluation of the Effectiveness of Automatic Rule-Based Transformations for Safety-Critical Applications.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

Evaluating System Dependability in a Co-Design Framework.
Proceedings of the 2000 Design, 2000

Automatic test bench generation for simulation-based validation.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999
Fault Injection for Embedded Microprocessor-based Systems.
J. UCS, 1999

Evaluating the Fault Tolerance Capabilities of Embedded Systems via BDM .
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

FlexFi: A Flexible Fault Injection Environment for Microprocessor-Based Systems.
Proceedings of the Computer Safety, 1999

ALPS: A Peak Power Estimation Tool for Sequential Circuits.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Test Pattern Generation Under Low Power Constraints.
Proceedings of the Evolutionary Image Analysis, 1999

Soft-Error Detection through Software Fault-Tolerance Techniques.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Optimal Vector Selection for Low Power BIST.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

1998
EXFI: a low-cost fault injection system for embedded microprocessor-based boards.
ACM Trans. Design Autom. Electr. Syst., 1998

The training environment for the course on microprocessor systems at the Politecnico di Torino.
Proceedings of the 1998 workshop on Computer architecture education, 1998

A Test Pattern Generation Methodology for Low-Power Consumption.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

A fault injection environment for microprocessor-based boards.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

An Integrated HW and SW Fault Injection Environment for Real-Time Systems.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

1997
SAARA: a simulated annealing algorithm for test pattern generation for digital circuits.
Proceedings of the 1997 ACM symposium on Applied Computing, 1997

Exploiting Symbolic Techniques within Genetic Algorithms for Power Optimization.
Proceedings of the 9th International Conference on Tools with Artificial Intelligence, 1997

GA-Based Performance Analysis of Network Protocols.
Proceedings of the 9th International Conference on Tools with Artificial Intelligence, 1997

A new Approach for Initialization Sequences Computation for Synchronous Sequential Circuits.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Boolean Function Manipulation on a Parallel System Using BDDs.
Proceedings of the High-Performance Computing and Networking, 1997

Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

New static compaction techniques of test sequences for sequential circuits.
Proceedings of the European Design and Test Conference, 1997

A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs.
Proceedings of the European Design and Test Conference, 1997

Simulation-based verification of network protocols performance.
Proceedings of the Advances in Hardware Design and Verification, 1997

Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

Guaranteeing Testability in Re-encoding for Low Power.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996
GALLO: a genetic algorithm for floorplan area optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Exploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Cicuits.
Proceedings of the Parallel Problem Solving from Nature, 1996

Partial Scan Flip Flop Selection for Simulation-Based Sequential ATPGs.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Comparing Topological, Symbolic and GA-based ATPGs: An Experimental Approach.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

A Cellular Genetic Algorithm for the Floorplan Area Optimization Problem on a SIMD Architecture.
Proceedings of the High-Performance Computing and Networking, 1996

Using Parallel Genetic Algorithms for Solving the Min-Cut Problem.
Proceedings of the High-Performance Computing and Networking, 1996

A Parallel Genetic Algorithm for Automatic Generation of Test Sequences for Digital Circuits.
Proceedings of the High-Performance Computing and Networking, 1996

Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experiment.
Proceedings of the conference on European design automation, 1996

On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications.
Proceedings of the Dependable Computing, 1996

Advanced Techniques for GA-based sequential ATPGs.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
A portable ATPG tool for parallel and distributed systems.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

An improved data parallel algorithm for Boolean function manipulation using BDDs.
Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing (PDP '95), 1995

Exploiting massively parallel architectures for the solution of diffusion and propagation problems.
Proceedings of the High-Performance Computing and Networking, 1995

A PVM tool for automatic test generation on parallel and distributed systems.
Proceedings of the High-Performance Computing and Networking, 1995

GARDA: a diagnostic ATPG for large synchronous sequential circuits.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
A BDD Package For A Massively Parallel SIMD Architecture.
Proceedings of the Second Euromicro Workshop on Parallel and Distributed Processing, 1994

An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

GATTO: An Intelligent Tool for Automatic Test Pattern Generation for Digital Circuits.
Proceedings of the Sixth International Conference on Tools with Artificial Intelligence, 1994

A Genetic Algorithm for Floorplan Area Optimization.
Proceedings of the First IEEE Conference on Evolutionary Computation, 1994

Floorplan area optimization using genetic algorithms.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

1993
An experimental analysis of the effects of migration in parallel genetic algorithms.
Proceedings of the 1993 Euromicro Workshop on Parallel and Distributed Processing, 1993


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