Ou He

According to our database, Ou He authored at least 8 papers between 2007 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2012

UNISM: Unified Scheduling and Mapping for General Networks on Chip.

Ou He, Sheqin Dong, Wooyoung Jang, Jinian Bian, David Z. Pan

IEEE Trans. Very Large Scale Integr. Syst., 2012

2011

Buffer Planning for IP Placement Using Sliced-LFF.

Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto

VLSI Design, 2011

Novel and efficient min cut based voltage assignment in gate level.

Tao Lin, Sheqin Dong, Song Chen, Yuchun Ma, Ou He, Satoshi Goto

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Chemical-mechanical polishing aware application-specific 3D NoC design.

Wooyoung Jang, Ou He, Jae-Seok Yang, David Z. Pan

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010

Bus via reduction based on floorplan revising.

Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2008

A novel fixed-outline floorplanner with zero deadspace for hierarchical design.

Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Symmetry constraint based on mismatch analysis for analog layout in SOI technology.

Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

An effective buffer planning algorithm for IP based fixed-outline SOC placement.

Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007