Xianlong Hong

According to our database1, Xianlong Hong authored at least 252 papers between 1992 and 2011.

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Bibliography

2011
Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs.
IEICE Transactions, 2011

Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
ECP- and CMP-Aware Detailed Routing Algorithm for DFM.
IEEE Trans. VLSI Syst., 2010

An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement.
IEEE Trans. VLSI Syst., 2010

Effective congestion reduction for IC package substrate routing.
ACM Trans. Design Autom. Electr. Syst., 2010

Thermal Impacts of Leakage Power in 2D/3D floorplanning.
Journal of Circuits, Systems, and Computers, 2010

Efficient Power Network Analysis with Modeling of Inductive Effects.
IEICE Transactions, 2010

Simultaneous slack budgeting and retiming for synchronous circuits optimization.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Substrate Topological Routing for High-Density Packages.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

An MTCMOS technology for low-power physical design.
Integration, 2009

Thermal aware placement in 3D ICs using quadratic uniformity modeling approach.
Integration, 2009

Efficient Partial Reluctance Extraction for Large-Scale Regular Power Grid Structures.
IEICE Transactions, 2009

Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation.
IEICE Transactions, 2009

A single layer zero skew clock routing in X architecture.
Science in China Series F: Information Sciences, 2009

Integrated interlayer via planning and pin assignment for 3D ICs.
Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

Modern Floorplanning with Boundary Clustering Constraint.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Efficient power network analysis with complete inductive modeling.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Incremental power optimization for multiple supply voltage design.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Simultaneous buffer and interlayer via planning for 3D floorplanning.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Cell shifting aware of wirelength and overlap.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Diffusion-driven congestion reduction for substrate topological routing.
Proceedings of the 2009 International Symposium on Physical Design, 2009

Buffer Planning for 3D ICs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Multi-objective Floorplanning Based on Fuzzy Logic.
Proceedings of the Sixth International Conference on Fuzzy Systems and Knowledge Discovery, 2009

An efficient decoupling capacitance optimization using piecewise polynomial models.
Proceedings of the Design, Automation and Test in Europe, 2009

Fast placement for large-scale hierarchical FPGAs.
Proceedings of the 11th International Conference on Computer-Aided Design and Computer Graphics, 2009

Statistical modeling and analysis of chip-level leakage power by spectral stochastic method.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

A novel thermal optimization flow using incremental floorplanning for 3D ICs.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Statistical Analysis of On-Chip Power Delivery Networks Considering Lognormal Leakage Current Variations With Spatial Correlation.
IEEE Trans. on Circuits and Systems, 2008

Random Walk Guided Decap Embedding for Power/Ground Network Optimization.
IEEE Trans. on Circuits and Systems, 2008

Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Fashion: A Fast and Accurate Solution to Global Routing Problem.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Zero skew clock routing in X-architecture based on an improved greedy matching algorithm.
Integration, 2008

A full-scale solution to the rectilinear obstacle-avoiding Steiner problem.
Integration, 2008

Large scale P/G grid transient simulation using hierarchical relaxed approach.
Integration, 2008

Efficient range pattern matching algorithm for process-hotspot detection.
IET Circuits, Devices & Systems, 2008

Early Stage Power Supply Planning: A Heuristic Method for Codesign of Power/Ground Network and Floorplan.
IEICE Transactions, 2008

Low Power Gated Clock Tree Driven Placement.
IEICE Transactions, 2008

Dummy Fill Aware Buffer Insertion after Layer Assignment Based on an Effective Estimation Model.
IEICE Transactions, 2008

Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage.
IEICE Transactions, 2008

Application of optical proximity correction technology.
Science in China Series F: Information Sciences, 2008

Full-chip routing system for reducing Cu CMP & ECP variation.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

DFM Based Detailed Routing Algorithm for ECP and CMP.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

IPOSA: A Novel Slack Distribution Algorithm for Interconnect Power Optimization.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Activity and register placement aware gated clock network design.
Proceedings of the 2008 International Symposium on Physical Design, 2008

Leakage power optimization for clock network using dual-Vth technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Gate planning during placement for gated clock network.
Proceedings of the 26th International Conference on Computer Design, 2008

A novel performance driven power gating based on distributed sleep transistor network.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation.
Proceedings of the FPL 2008, 2008

Topological routing to maximize routability for package substrate.
Proceedings of the 45th Design Automation Conference, 2008

Low power clock buffer planning methodology in F-D placement for large scale circuit design.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Heuristic power/ground network and floorplan co-design method.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Symmetry constraint based on mismatch analysis for analog layout in SOI technology.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Vertical via design techniques for multi-layered P/G networks.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

LP based white space redistribution for thermal via planning and performance optimization in 3D ICs.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Wire density driven top-down global placement for CMP variation control.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

lambda-OAT: lambda-Geometry Obstacle-Avoiding Tree Construction With O(nlog n) Complexity.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

A Yield-Driven Gridless Router.
J. Comput. Sci. Technol., 2007

APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement.
Integration, 2007

An efficient quadratic placement based on search space traversing technology.
Integration, 2007

Partitioning-based decoupling capacitor budgeting via sequence of linear programming.
Integration, 2007

Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration.
IEICE Transactions, 2007

Voltage Island Generation in Cell Based Dual-Vdd Design.
IEICE Transactions, 2007

An accurate and efficient probabilistic congestion estimation model in x architecture.
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

CMP-aware Maze Routing Algorithm for Yield Enhancement.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Interconnect Power Optimization Based on Timing Analysis.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Power Delivery Aware Floorplanning for Voltage Island Designs.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Congestion Driven Buffer Planning for X-Architecture.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A Fast 3D-BSG Algorithm for 3D Packing Problem.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Unified Quadratic Programming Approach For 3-D Mixed Mode Placement.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Effective Acceleration of Iterative Slack Distribution Process.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

New timing and routability driven placement algorithms for FPGA synthesis.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Physical aware clock skew rescheduling.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Dummy fill aware buffer insertion during routing.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

An effective buffer planning algorithm for IP based fixed-outline SOC placement.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Statistical model order reduction for interconnect circuits considering spatial correlations.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning.
Proceedings of the 10th International Conference on Computer-Aided Design and Computer Graphics, 2007

Simultaneous Switching Noise Consideration for Power/Ground Network Optimization.
Proceedings of the 10th International Conference on Computer-Aided Design and Computer Graphics, 2007

Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Logic and Layout Aware Voltage Island Generation for Low Power Design.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Legitimate Skew Clock Routing with Buffer Insertion.
VLSI Signal Processing, 2006

Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration.
ACM Trans. Design Autom. Electr. Syst., 2006

Multilevel Routing With Redundant Via Insertion.
IEEE Trans. on Circuits and Systems, 2006

Obstacle-avoiding rectilinear minimum-delay Steiner tree construction toward IP-block-based SOC design.
IEEE Trans. on Circuits and Systems, 2006

Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization.
IEEE Trans. on Circuits and Systems, 2006

VLSI Block Placement With Alignment Constraints.
IEEE Trans. on Circuits and Systems, 2006

Power/Ground Network Optimization Considering Decap Leakage Currents.
IEEE Trans. on Circuits and Systems, 2006

A Two-Step Heuristic Algorithm for Minimum-Crosstalk Routing Resource Assignment.
IEEE Trans. on Circuits and Systems, 2006

Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

General Floorplans with L/T-Shaped Blocks Using Corner Block List.
J. Comput. Sci. Technol., 2006

ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm.
J. Comput. Sci. Technol., 2006

Priority-Based Routing Resource Assignment Considering Crosstalk.
J. Comput. Sci. Technol., 2006

Time-domain analysis methodology for large-scale RLC circuits and its applications.
Science in China Series F: Information Sciences, 2006

Floorplanning by A Revised 3-D Corner Block List with sub-C+-tree.
Proceedings of the 2006 Joint Conference on Information Sciences, 2006

Stochastic Local Search Using the Search Space Smoothing Meta-Heuristic: A Case Study.
Proceedings of the 2006 Joint Conference on Information Sciences, 2006

A Novel Tour Construction Heuristic for Traveling Salesman Problem Using LFF Principle.
Proceedings of the 2006 Joint Conference on Information Sciences, 2006

Clock Skew Scheduling Under Process Variations.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

High accurate pattern based precondition method for extremely large power/ground grid analysis.
Proceedings of the 2006 International Symposium on Physical Design, 2006

Integrating dynamic thermal via planning with 3D floorplanning algorithm.
Proceedings of the 2006 International Symposium on Physical Design, 2006

An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane.
Proceedings of the 2006 International Symposium on Physical Design, 2006

A novel low-power physical design methodology for MTCMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Congestion-driven W-shape multilevel full-chip routing framework.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

On handling the fixed-outline constraints of floorplanning using less flexibility first principles.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Performance and power aware buffered tree construction.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High performance clock routing in X-architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A novel technique integrating buffer insertion into timing driven placement.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Floorplanning for 2.5-D system integration using multi-layer-BSG structure.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Buffer planning based on block exchanging.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Efficient process-hotspot detection using range pattern matching.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

CDCTree: novel obstacle-avoiding routing tree construction based on current driven circuit model.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Efficient early stage resonance estimation techniques for C4 package.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Signal-path driven partition and placement for analog circuit.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

DraXRouter: global routing in X-Architecture with dynamic resource assignment.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

DFM-aware Routing for Yield Enhancement.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Spanning graph-based nonrectilinear steiner tree algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Buffer planning as an Integral part of floorplanning with consideration of routing congestion.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Crosstalk-Aware Routing Resource Assignment.
J. Comput. Sci. Technol., 2005

Shielding Area Optimization Under the Solution of Interconnect Crosstalk.
J. Comput. Sci. Technol., 2005

Modeling and Analysis of Mesh Tree Hybrid Power/Ground Networks with Multiple Voltage Supply in Time Domain.
J. Comput. Sci. Technol., 2005

A Fast Delay Computation for the Hybrid Structured Clock Network.
IEICE Transactions, 2005

Navigating Register Placement for Low Power Clock Network Design.
IEICE Transactions, 2005

Crosstalk and Congestion Driven Layer Assignment Algorithm.
IEICE Transactions, 2005

Reliable buffered clock tree routing algorithm with process variation tolerance.
Science in China Series F: Information Sciences, 2005

A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design.
Proceedings of the Embedded Computer Systems: Architectures, 2005

Efficient Simulation of Power/Ground Networks with Package and Vias.
Proceedings of the Integrated Circuit and System Design, 2005

A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design.
Proceedings of the Integrated Circuit and System Design, 2005

Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Buffer Planning Algorithm Based on Partial Clustered Floorplanning.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

A new approach based on LFF for optimization of dynamic hardware reconfigurations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An efficient algorithm for buffered routing tree construction under fixed buffer locations with accurate delay models.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Timing-driven global routing with efficient buffer insertion.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Zero skew clock routing with tree topology construction using simulated annealing method.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Interconnect delay optimization via high level re-synthesis after floorplanning.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Performance constrained floorplanning based on partial clustering [IC layout].
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Fixed-outline floorplanning with constraints through instance augmentation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

VLSI block placement with alignment constraints based on corner block list.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A global interconnect optimization algorithm under accurate delay model using solution space smoothing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Integrated routing resource assignment for RLC crosstalk minimization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Hybrid Genetic Algorithm and Application to the Crosstalk Aware Track Assignment Problem.
Proceedings of the Advances in Natural Computation, First International Conference, 2005

A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design.
Proceedings of the Embedded Software and Systems, Second International Conference, 2005

Multi-stage Detailed Placement Algorithm for Large-Scale Mixed-Mode Layout Design.
Proceedings of the Computational Science and Its Applications, 2005

Improved multilevel routing with redundant via placement for yield and reliability.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

An improved direct boundary element method for substrate coupling resistance extraction.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

A new algorithm for layout of dark field alternating phase shifting masks.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Fixed-outline floorplanning based on common subsequence.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

A New Buffer Planning Algorithm Based on Room Resizing.
Proceedings of the Embedded and Ubiquitous Computing, 2005

Navigating registers in placement for clock network minimization.
Proceedings of the 42nd Design Automation Conference, 2005

Partitioning-based approach to fast on-chip decap budgeting and minimization.
Proceedings of the 42nd Design Automation Conference, 2005

An efficient algorithm to fixed-outline floorplanning based on instance augmentation.
Proceedings of the 9th International Conference on Computer-Aided Design and Computer Graphics, 2005

Analysis of buffered hybrid structured clock networks.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

LFF algorithm for heterogeneous FPGA floorplanning.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

The polygonal contraction heuristic for rectilinear Steiner tree construction.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

An improved P-admissible floorplan representation based on Corner Block List.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Register placement for low power clock network.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Clock network minimization methodology based on incremental placement.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

An-OARSMan: obstacle-avoiding routing tree construction with good length performance.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

VLSI on-chip power/ground network optimization considering decap leakage currents.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Relaxed hierarchical power/ground grid analysis.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Via-Aware Global Routing for Good VLSI Manufacturability and High Yield.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
Corner block list representation and its application to floorplan optimization.
IEEE Trans. on Circuits and Systems, 2004

Area minimization of power distribution network using efficient nonlinear programming techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

UTACO: a unified timing and congestion optimization algorithm for standard cell global routing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Leakage Current Estimation of CMOS Circuit with Stack Effect.
J. Comput. Sci. Technol., 2004

Fast Evaluation of Bounded Slice-Line Grid.
J. Comput. Sci. Technol., 2004

Corner block list representation and its application with boundary constraints.
Science in China Series F: Information Sciences, 2004

A buffer planning algorithm for chip-level floorplanning.
Science in China Series F: Information Sciences, 2004

An Efficient Low-Degree RMST Algorithm for VLSI/ULSI Physical Design.
Proceedings of the Integrated Circuit and System Design, 2004

Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery.
Proceedings of the Integrated Circuit and System Design, 2004

Transient Analysis of On-Chip Power Distribution Networks Using Equivalent Circuit Modeling.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Quick and effective buffered legitimate skew clock routing.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Shielding area optimization under the solution of interconnect crosstalk.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Performance and RLC crosstalk driven global routing.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Crosstalk driven routing resource assignment.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Algorithm for yield driven correction of layout.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Layer assignment algorithm for RLC crosstalk minimization.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Partial random walk for large linear network analysis.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Module placement based on quadratic programming and rectangle packing using less flexibility first principle.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Efficient octilinear Steiner tree construction based on spanning graphs.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Buffer allocation algorithm with consideration of routing congestion.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

A fast decoupling capacitor budgeting algorithm for robust on-chip power delivery.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

A buffer planning algorithm with congestion optimization.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
SSTT: Efficient Local Search for GSI Global Routing.
J. Comput. Sci. Technol., 2003

FaSa: A Fast and Stable Quadratic Placement Algorithm.
J. Comput. Sci. Technol., 2003

CNB: A Critical-Network-Based Timing Optimization Method for Standard Cell Global Routing.
J. Comput. Sci. Technol., 2003

Deterministic VLSI Block Placement Algorithm Using Less Flexibility First Principle.
J. Comput. Sci. Technol., 2003

An integrated floorplanning with an efficient buffer planning algorithm.
Proceedings of the 2003 International Symposium on Physical Design, 2003

Arbitrary convex and concave rectilinear block packing based on corner block list.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Combining clustering and partitioning in quadratic placement.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Algorithms for analog VLSI 2D stack generation and block merging.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Evaluating a bounded slice-line grid assignment in O(nlogn) time.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Dynamic global buffer planning optimization based on detail block locating and congestion analysis.
Proceedings of the 40th Design Automation Conference, 2003

A novel timing-driven global routing algorithm considering coupling effects for high performance circuit design.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

BBE: hierarchical computation of 3-D interconnect capacitance with BEM block extraction.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Congestion driven incremental placement algorithm for standard cell layout.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

A path-based timing-driven quadratic placement algorithm.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

VLSI module placement with pre-placed modules and considering congestion using solution space smoothing.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

A buffer planning algorithm based on dead space redistribution.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
An Optimum Placement Search Algorithm Based on Extended Corner Block List.
J. Comput. Sci. Technol., 2002

A multi-step standard-cell placement algorithm of optimizing timing and congestion behavior.
Science in China Series F: Information Sciences, 2002

An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

A novel and efficient timing-driven global router for standard cell layout design based on critical network concept.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Floorplanning with abutment constraints based on corner block list.
Integration, 2001

Area Minimization of Power Distribution Network Using Efficient Nonlinear Programming Techniques.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List.
Proceedings of the 38th Design Automation Conference, 2001

VLSI floorplanning with boundary constraints based on corner block list.
Proceedings of ASP-DAC 2001, 2001

A new congestion-driven placement algorithm based on cell inflation.
Proceedings of ASP-DAC 2001, 2001

VLSI block placement using less flexibility first principles.
Proceedings of ASP-DAC 2001, 2001

2000
Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

MMP: a novel placement algorithm for combined macro block and standard cell layout design.
Proceedings of ASP-DAC 2000, 2000

Area routing oriented hierarchical corner stitching with partial bin.
Proceedings of ASP-DAC 2000, 2000

Hierarchical computation of 3-D interconnect capacitance using direct boundary element method.
Proceedings of ASP-DAC 2000, 2000

A simplified hybrid method for calculating the frequency-dependent inductances of transmission lines with rectangular cross section.
Proceedings of ASP-DAC 2000, 2000

1999
Design and Optimization of Power/Ground Network for Cell-Based VLSIs with Macro Cells.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

A Timing-Driven Block Placer Based on Sequence Pair Model.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

A New Global Routing Algorithm Independent Of Net Ordering.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1997
TIGER: an efficient timing-driven global router for gate array and standard cell layout design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

VEAP: Global optimization based efficient algorithm for VLSI placement.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1993
An Efficient Timing-Driven Global Routing Algorithm.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

Performance-Driven Steiner Tree Algorithm for Global Routing.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
FARM: An Efficient Feed-Through Pin Assignment Algorithm.
Proceedings of the 29th Design Automation Conference, 1992


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