Sheqin Dong

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2018

Ordered Escape Routing with Consideration of Differential Pair and Blockage.

[BibT_eX]

[DOI]

Fengxian Jiao

ACM Trans. Design Autom. Electr. Syst., 2018

A Novel Mixed-Size Fixed-Outline Floorplacement Algorithm.

[BibT_eX]

[DOI]

Qian Chen

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

TSF3D: MSV-Driven Power Optimization for Application-Specific 3D Network-on-Chip.

[BibT_eX]

[DOI]

Fengxian Jiao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

2016

Ordered Escape routing for grid pin array based on Min-cost Multi-commodity Flow.

[BibT_eX]

[DOI]

Fengxian Jiao

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Delay-Driven and Antenna-Aware Layer Assignment in Global Routing Under Multitier Interconnect Structure.

[BibT_eX]

[DOI]

Jianchang Ao

Fuqi Luo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014

Mixed-Crossing-Avoided Escape Routing of Mixed-Pattern Signals on Staggered-Pin-Array PCBs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Multi-Voltage and Level-Shifter Assignment Driven Floorplanning.

[BibT_eX]

[DOI]

Bei Yu

Satoshi Goto

CoRR, 2014

Post-floorplanning power optimization for MSV-driven application specific NoC design.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Multi-bend bus-driven floorplanning considering fixed-outline constraints.

[BibT_eX]

[DOI]

Wenxu Sheng

Integr., 2013

Escape routing of mixed-pattern signals based on staggered-pin-array PCBs.

[BibT_eX]

[DOI]

Huaxi Wang

Proceedings of the International Symposium on Physical Design, 2013

Delay-driven layer assignment in global routing under multi-tier interconnect structure.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2013

Power optimization for application-specific 3D network-on-chip with multiple supply voltages.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

UNISM: Unified Scheduling and Mapping for General Networks on Chip.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2012

Novel Voltage Choice and Min-Cut Based Assignment for Dual-VDD System.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Voltage island-driven power optimization for application specific network-on-chip design.

[BibT_eX]

[DOI]

Satoshi Goto

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Linear optimal one-sided single-detour algorithm for untangling twisted bus.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Buffer Planning for IP Placement Using Sliced-LFF.

[BibT_eX]

[DOI]

VLSI Design, 2011

Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Application-specific Network-on-Chip synthesis: Cluster generation and network component insertion.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Novel and efficient min cut based voltage assignment in gate level.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Network flow-based simultaneous retiming and slack budgeting for low power design.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Through-Silicon-Via assignment for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010

Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs.

[BibT_eX]

[DOI]

Xu He

Yuchun Ma

Integr., 2010

Fixed outline multi-bend bus driven floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Wirelength-driven force-directed 3D FPGA placement.

[BibT_eX]

[DOI]

Wentao Sui

Jinian Bian

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

A revisit to voltage partitioning problem.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Bus via reduction based on floorplan revising.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Floorplanning and topology generation for application-specific network-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Voltage and Level-Shifter Assignment Driven Floorplanning.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Integrated interlayer via planning and pin assignment for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

Simultaneous buffer and interlayer via planning for 3D floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Buffer Planning for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Voltage-island driven floorplanning considering level-shifter positions.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008

Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A novel fixed-outline floorplanner with zero deadspace for hierarchical design.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

HyMacs: hybrid memory access optimization based on custom-instruction scheduling.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Cache miss reduction through hardware-assisted loop optimization.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on CSCW in Design, 2008

Symmetry constraint based on mismatch analysis for analog layout in SOI technology.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

LP based white space redistribution for thermal via planning and performance optimization in 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement.

[BibT_eX]

[DOI]

Yaoguang Wei

Integr., 2007

An accurate and efficient probabilistic congestion estimation model in x architecture.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

Interconnect Power Optimization Based on Timing Analysis.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Congestion Driven Buffer Planning for X-Architecture.

[BibT_eX]

[DOI]

Hongjie Bai

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A Fast 3D-BSG Algorithm for 3D Packing Problem.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

An effective buffer planning algorithm for IP based fixed-outline SOC placement.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

A Fast Custom Instructions Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design.

[BibT_eX]

[DOI]

Kang Zhao

Jinian Bian

Proceedings of the 11th International Conference on Computer Supported Cooperative Work in Design, 2007

Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

VLSI Block Placement With Alignment Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

General Floorplans with L/T-Shaped Blocks Using Corner Block List.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2006

A Heterogeneous Dependency Graph as Intermediate Representation for Instruction Set Customization.

[BibT_eX]

[DOI]

Kang Zhao

Jinian Bian

Proceedings of the 2006 Joint Conference on Information Sciences, 2006

Floorplanning by A Revised 3-D Corner Block List with sub-C+-tree.

[BibT_eX]

[DOI]

Proceedings of the 2006 Joint Conference on Information Sciences, 2006

Stochastic Local Search Using the Search Space Smoothing Meta-Heuristic: A Case Study.

[BibT_eX]

[DOI]

Proceedings of the 2006 Joint Conference on Information Sciences, 2006

A Novel Tour Construction Heuristic for Traveling Salesman Problem Using LFF Principle.

[BibT_eX]

[DOI]

Proceedings of the 2006 Joint Conference on Information Sciences, 2006

On handling the fixed-outline constraints of floorplanning using less flexibility first principles.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Floorplanning for 2.5-D system integration using multi-layer-BSG structure.

[BibT_eX]

[DOI]

Shuyi Zheng

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Buffer planning based on block exchanging.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Signal-path driven partition and placement for analog circuit.

[BibT_eX]

[DOI]

Di Long

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

Buffer planning as an Integral part of floorplanning with consideration of routing congestion.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Buffer Planning Algorithm Based on Partial Clustered Floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

A new approach based on LFF for optimization of dynamic hardware reconfigurations.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Performance constrained floorplanning based on partial clustering [IC layout].

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit.

[BibT_eX]

[DOI]

Di Long

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Fixed-outline floorplanning with constraints through instance augmentation.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

VLSI block placement with alignment constraints based on corner block list.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Fixed-outline floorplanning based on common subsequence.

[BibT_eX]

[DOI]

Rong Liu

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

A New Buffer Planning Algorithm Based on Room Resizing.

[BibT_eX]

[DOI]

Proceedings of the Embedded and Ubiquitous Computing, 2005

An efficient algorithm to fixed-outline floorplanning based on instance augmentation.

[BibT_eX]

[DOI]

Rong Liu

Proceedings of the 9th International Conference on Computer-Aided Design and Computer Graphics, 2005

LFF algorithm for heterogeneous FPGA floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

An improved P-admissible floorplan representation based on Corner Block List.

[BibT_eX]

[DOI]

Renshen Wang