Pandy Kalimuthu

According to our database1, Pandy Kalimuthu authored at least 2 papers between 2019 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Efficient Hierarchical Post-Silicon Validation and Debug.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

2019
Techniques for Debug of Low Power SoCs.
Proceedings of the 20th International Workshop on Microprocessor/SoC Test, 2019


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