Spencer K. Millican

J. Electron. Test., 2022

2021

Special Session - Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator.

[BibT_eX]

[DOI]

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

A Pragmatic Quaternary FPGA Implemented with Floating Gate Memories.

[BibT_eX]

[DOI]

Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021

Simulating and Evaluating a Quaternary Logic FPGA Based on Floating-gate Memories and Voltage Division.

[BibT_eX]

[DOI]

Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

Unsupervised Learning in Test Generation for Digital Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE European Test Symposium, 2021

A study of transistor degradation in cyber-physical system control devices: work-in-progress.

[BibT_eX]

[DOI]

SueAnne Griffith

Proceedings of the CODES/ISSS 2021, 2021

2020

Improved Pseudo-Random Fault Coverage Through Inversions: a Study on Test Point Architectures.

[BibT_eX]

[DOI]

J. Electron. Test., 2020

Special Session: Survey of Test Point Insertion for Logic Built-in Self-test.

[BibT_eX]

[DOI]

Yang Sun

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Calculating Signal Controllability using Neural Networks: Improvements to Testability Analysis and Test Point Insertion.

[BibT_eX]

[DOI]

Joshua Immanuel

Proceedings of the 29th IEEE North Atlantic Test Workshop, 2020

Machine Intelligence for Efficient Test Pattern Generation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2020

A Quaternary FPGA Architecture Using Floating Gate Memories.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019

Special Session: Delay Fault Testing - Present and Future.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Improved Random Pattern Delay Fault Coverage Using Inversion Test Points.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE North Atlantic Test Workshop, 2019

Techniques for Debug of Low Power SoCs.

[BibT_eX]

[DOI]

Sukhbinder Singh Takhar

Proceedings of the 20th International Workshop on Microprocessor/SoC Test, 2019

Test Point Insertion Using Artificial Neural Networks.

[BibT_eX]

[DOI]

Yang Sun

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Applying Neural Networks to Delay Fault Testing: Test Point Insertion and Random Circuit Training.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Asian Test Symposium, 2019

2015

Optimal Test Scheduling of Stacked Circuits under Various Hardware and Power Constraints.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on VLSI Design, 2015

2014

Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling.

[BibT_eX]

[DOI]

J. Electron. Test., 2014

A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

CryptIP: An Approach for Encrypting Intellectual Property Cores with Simulation Capabilities.

[BibT_eX]

[DOI]

Parameswaran Ramanathan

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2013

Formulating Optimal Test Scheduling Problem with Dynamic Voltage and Frequency Scaling.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

2012

Linear Programming Formulations for Thermal-Aware Test Scheduling of 3D-Stacked Integrated Circuits.

[BibT_eX]

[DOI]