Eric Rentschler

According to our database1, Eric Rentschler authored at least 4 papers between 2013 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2019
Techniques for Debug of Low Power SoCs.
Proceedings of the 20th International Workshop on Microprocessor/SoC Test, 2019

2016
Special panel session IIB: "System validation and silicon debug - Is standardization possible?".
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

2015
Quick error detection tests with fast runtimes for effective post-silicon validation and debug.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2013
Evolution of Graphics Northbridge Test and Debug Architectures Across Four Generations of AMD ASICs.
IEEE Des. Test, 2013


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