Priyadarsan Patra

According to our database, Priyadarsan Patra authored at least 28 papers between 1994 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2020

In silico ranking of phenolics for therapeutic effectiveness on cancer stem cells.

Monalisa Mandal, Sanjeeb Kumar Sahoo, Priyadarsan Patra, Saurav Mallik, Zhongming Zhao

BMC Bioinform., 2020

Enabling Hardware Performance Counters for Microkernel-Based Virtualization on Embedded Systems.

Deepa Mathew, Bijoy Antony Jose, Jimson Mathew, Priyadarsan Patra

IEEE Access, 2020

2019

Performance Analysis of Microkernel Based Virtualization Techniques on Embedded Systems.

Deepa Mathew, Bijoy Antony Jose, Priyadarsan Patra

J. Low Power Electron., 2019

Selected Articles from the ISED 2018 Conference.

Jimson Mathew, Bijoy Antony Jose, Priyadarsan Patra

J. Low Power Electron., 2019

Techniques for Debug of Low Power SoCs.

Sankaran M. Menon, Ashish Gupta, Chinna Prudvi, Rolf Kühnis, Sukhbinder Singh Takhar, Spencer K. Millican, Eric Rentschler, Pandy Kalimuthu, Preeti Ranjan Panda, Priyadarsan Patra

Proceedings of the 20th International Workshop on Microprocessor/SoC Test, 2019

2017

Selected Articles from the IEEE ISED 2016 Conference.

Jimson Mathew, Hafizur Rahaman, Priyadarsan Patra, Dhiraj K. Pradhan

J. Low Power Electron., 2017

2015

Selected Articles from the IEEE ISED 2014 Conference.

Jimson Mathew, Hafizur Rahaman, Priyadarsan Patra, Dhiraj K. Pradhan

J. Low Power Electron., 2015

Fabrics on Die: Where Function, Debug and Test Meet.

Priyadarsan Patra, Chinna Prudvi

Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

2014

Selected Articles from the IEEE ISED 2013 Conference.

Jimson Mathew, A. Prasad Vinod, Priyadarsan Patra

J. Low Power Electron., 2014

2013

Selected Articles from the IEEE ISED 2012 Conference.

Jimson Mathew, Priyadarsan Patra

J. Low Power Electron., 2013

Observability-aware Directed Test Generation for Soft Errors and Crosstalk Faults.

Kanad Basu, Prabhat Mishra, Priyadarsan Patra

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Dynamic Selection of Trace Signals for Post-Silicon Debug.

Kanad Basu, Prabhat Mishra, Priyadarsan Patra, Amir Nahir, Allon Adir

Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013

Double Layer Perceptron Synchronized Computational Intelligence Guided Fractal Triangle Based Cryptographic Technique for Secured Communication (DLPFT).

Arindam Sarkar, J. K. Mandal, Priyadarsan Patra

Proceedings of the 2013 International Symposium on Electronic System Design, 2013

2012

Constrained signal selection for post-silicon validation.

Kanad Basu, Prabhat Mishra, Priyadarsan Patra

Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

2011

Efficient combination of trace and scan signals for post silicon validation and debug.

Kanad Basu, Prabhat Mishra, Priyadarsan Patra

Proceedings of the 2011 IEEE International Test Conference, 2011

Bee Colony Inspired Metamodeling Based Fast Optimization of a Nano-CMOS PLL.

Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos, Priyadarsan Patra

Proceedings of the International Symposium on Electronic System Design, 2011

2009

A PVT aware accurate statistical logic library for high- metal-gate nano-CMOS.

Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos, Priyadarsan Patra

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008

Impact of Process and Temperature Variations on Network-on-Chip Design Exploration.

Bin Li, Li-Shiuan Peh, Priyadarsan Patra

Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Runtime Validation of Transactional Memory Systems.

Kaiyu Chen, Sharad Malik, Priyadarsan Patra

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Runtime validation of memory ordering using constraint graph checking.

Kaiyu Chen, Sharad Malik, Priyadarsan Patra

Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

2007

On the cusp of a validation wall.

Priyadarsan Patra

IEEE Des. Test Comput., 2007

2003

ESTIMA: an architectural-level power estimator for multi-ported pipelined register files.

Kavel M. Büyüksahin, Priyadarsan Patra, Farid N. Najm

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

2002

A System-Level Solution to Domino Synthesis with 2 GHz Application.

B. Chappell, Xinning Wang, Priyadarsan Patra, Prashant Saxena, J. Vendrell, Satyanarayan Gupta, S. Varadarajan, W. Gomes, S. Hussain, H. Krishnamurthy, M. Venkateshmurthy, S. Jain

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

1997

Delay Insensitive Logic for RSFQ Superconductor Technology.

Priyadarsan Patra, Stanislav Polonsky, Donald S. Fussell

Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

1996

Efficient Delay-Insensitive RSFQ Circuits.

Priyadarsan Patra, Donald S. Fussell

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

1995

Fully asynchronous, robust, high-throughput arithmetic structures.

Priyadarsan Patra, Donald S. Fussell

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Power-efficient delay-insensitive codes for data transmission.

Priyadarsan Patra, Donald S. Fussell

Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995

1994

Efficient building blocks for delay insensitive circuits.

Priyadarsan Patra, Donald S. Fussell

Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1994