Paul Rigge
Orcid: 0000-0003-4900-6473Affiliations:
- University of California at Berkeley, Electrical Engineering and Computer Sciences (EECS) Department, Berkeley, CA, USA
According to our database1,
Paul Rigge
authored at least 17 papers
between 2012 and 2020.
Collaborative distances:
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Bibliography
2020
Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs.
IEEE Micro, 2020
Wireless Channel Dynamics for Relay Selection under Ultra-Reliable Low-Latency Communication.
Proceedings of the 31st IEEE Annual International Symposium on Personal, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.
IEEE J. Solid State Circuits, 2019
IEEE J. Solid State Circuits, 2019
Wireless Channel Dynamics and Robustness for Ultra-Reliable Low-Latency Communications.
IEEE J. Sel. Areas Commun., 2019
2018
Proceedings of the 2018 IEEE International Symposium on Information Theory, 2018
A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
IEEE Trans. Wirel. Commun., 2017
2016
Proceedings of the IEEE Wireless Communications and Networking Conference Workshops, 2016
2015
Proceedings of the 2015 IEEE International Conference on Communications, 2015
2012
Performance of FORTRAN and C GPU Extensions for a Benchmark Suite of Fourier Pseudospectral Algorithms.
CoRR, 2012