Woo-Rham Bae
Orcid: 0000-0002-9274-0182Affiliations:
- Ayar Labs, Santa Clara, CA, USA
- University of California Berkeley, Department of Electrical Engineering and Computer Sciences, CA, USA
- Seoul National University, South Korea (PhD 2016)
According to our database1,
Woo-Rham Bae
authored at least 47 papers
between 2012 and 2022.
Collaborative distances:
Collaborative distances:
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Bibliography
2022
IEEE J. Solid State Circuits, 2022
Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures.
IEEE Access, 2022
2021
LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
PeerJ Comput. Sci., 2021
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
State-of-the-Art Circuit Techniques for Low-Jitter Phase-Locked Loops: Advanced Performance Benchmark FOM Based on an Extensive Survey.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
Weight Update Generation Circuit Utilizing Phase Noise of Integrated Complementary Metal-Oxide-Semiconductor Ring Oscillator for Memristor Crossbar Array Neural Network-Based Stochastic Learning.
Adv. Intell. Syst., 2020
2019
A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.
IEEE J. Solid State Circuits, 2019
IEEE J. Solid State Circuits, 2019
A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards.
IEEE Trans. Ind. Electron., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A Variation-Tolerant, Sneak-Current-Compensated Readout Scheme for Cross-Point Memory Based on Two-Port Sensing Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS.
IEEE J. Solid State Circuits, 2018
A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2017
A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and G<sub>m</sub>-Regulated Resistive-Feedback Driver.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Sensors, 2017
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
A 0.36 pJ/bit, 0.025 mm<sup>2</sup>, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A 1-pJ/bit, 10-Gb/s/ch Forwarded-Clock Transmitter Using a Resistive Feedback Inverter-Based Driver in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- G<sub>m</sub> Bias.
IEEE J. Solid State Circuits, 2016
A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS.
IEEE J. Solid State Circuits, 2016
A 800-Mb/s 0.89-pJ/b reference-less optical receiver with pulse-position-modulation scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A fully integrated 1-pJ/bit 10-Gb/s/ch forwarded-clock transmitter with a resistive feedback inverter based driver in 65-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process.
IEEE J. Solid State Circuits, 2015
A power-efficient 600-mV<sub>pp</sub> voltage-mode driver with independently matched pull-up and pull-down impedances.
Int. J. Circuit Theory Appl., 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection.
Proceedings of the ESSCIRC Conference 2015, 2015
A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line.
Proceedings of the ESSCIRC 2014, 2014
A study on using pulse generators to design a ring-VCO based bang-bang PLL/CDR with a consistent loop bandwidth.
Proceedings of the International Conference on Electronics, Information and Communications, 2014
A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2012
Proceedings of the International SoC Design Conference, 2012