Woo-Rham Bae

According to our database1, Woo-Rham Bae authored at least 38 papers between 2012 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Online presence:

On csauthors.net:

Bibliography

2019
A Real-Time, 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.
IEEE J. Solid State Circuits, 2019

A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance.
IEEE J. Solid State Circuits, 2019

Reference Spur Reduction Techniques for a Phase-Locked Loop.
IEEE Access, 2019

A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
A Supply-Scalable-Serializing Transmitter With Controllable Output Swing and Equalization for Next-Generation Standards.
IEEE Trans. Ind. Electron., 2018

A 32 Gb/s, 201 mW, MZM/EAM Cascode Push-Pull CML Driver in 65 nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Variation-Tolerant, Sneak-Current-Compensated Readout Scheme for Cross-Point Memory Based on Two-Port Sensing Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 6.7-11.2 Gb/s, 2.25 pJ/bit, Single-Loop Referenceless CDR With Multi-Phase, Oversampling PFD in 65-nm CMOS.
IEEE J. Solid State Circuits, 2018

A Real-Time, Analog/Digital Co-Designed 1.89-GHz Bandwidth, 175-kHz Resolution Sparse Spectral Analysis RISC-V SoC in 16-nm FinFET.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

BAG2: A process-portable framework for generator-based AMS circuit design.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018


2017
Use of Phase Delay Analysis for Evaluating Wideband Circuits: An Alternative to Group Delay Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A 28 Gb/s 1.6 pJ/b PAM-4 Transmitter Using Fractionally Spaced 3-Tap FFE and G<sub>m</sub>-Regulated Resistive-Feedback Driver.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection.
Sensors, 2017

A 27.1 mW, 7.5-to-11.1 Gb/s single-loop referenceless CDR with direct Up/dn control.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A 0.36 pJ/bit, 0.025 mm<sup>2</sup>, 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 1-pJ/bit, 10-Gb/s/ch Forwarded-Clock Transmitter Using a Resistive Feedback Inverter-Based Driver in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- G<sub>m</sub> Bias.
IEEE J. Solid State Circuits, 2016

A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS.
IEEE J. Solid State Circuits, 2016

A 800-Mb/s 0.89-pJ/b reference-less optical receiver with pulse-position-modulation scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A fully integrated 1-pJ/bit 10-Gb/s/ch forwarded-clock transmitter with a resistive feedback inverter based driver in 65-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process.
IEEE J. Solid State Circuits, 2015

A power-efficient 600-mV<sub>pp</sub> voltage-mode driver with independently matched pull-up and pull-down impedances.
Int. J. Circuit Theory Appl., 2015

A 10 Gb/s hybrid PLL-based forwarded clock receiver in 65-nm CMOS.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A low-power pulse position modulation transceiver.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection.
Proceedings of the ESSCIRC Conference 2015, 2015

A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

A 7.6 mW, 214-fs RMS jitter 10-GHz phase-locked loop for 40-Gb/s serial link transmitter based on two-stage ring oscillator in 65-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A 10-Gb/s 6-Vpp differential modulator driver in 65-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 0.36 pJ/bit, 12.5 Gb/s forwarded-clock receiver with a sample swapping scheme and a half-bit delay line.
Proceedings of the ESSCIRC 2014, 2014

A study on using pulse generators to design a ring-VCO based bang-bang PLL/CDR with a consistent loop bandwidth.
Proceedings of the International Conference on Electronics, Information and Communications, 2014

A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technology.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2012
Design of CMOS 5 Gb/s 4-PAM transceiver frontend for low-power memory interface.
Proceedings of the International SoC Design Conference, 2012


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