Pei-Yuan Chou

According to our database, Pei-Yuan Chou authored at least 7 papers between 2014 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2019

An All-Digital On-Chip Peak-to-Peak Jitter Measurement Circuit With Automatic Resolution Calibration for High PVT-Variation Resilience.

Pei-Yuan Chou, Jinn-Shyan Wang

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018

Near-Threshold CORDIC Design with Dynamic Circuitry for Long-Standby IoT Applications.

Pei-Yuan Chou, Ya-Bei Fang, Bo-Hao Chen, Chien-Tung Liu, Tay-Jyi Lin, Jinn-Shyan Wang

Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

2017

An all-n-type dynamic adder for ultra-low-leakage IoT devices.

Ya-Bei Fang, Pei-Yuan Chou, Bo-Hao Chen, Tay-Jyi Lin, Jinn-Shyan Wang

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

Design of an all-digital temperature sensor in 28 nm CMOS using temperature-sensitive delay cells and adaptive-1P calibration for error reduction.

Shang-Yi Li, Pei-Yuan Chou, Jinn-Shyan Wang

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture.

Jinn-Shyan Wang, Chun-Yuan Cheng, Pei-Yuan Chou, Tzu-Yi Yang

IEEE J. Solid State Circuits, 2015

Low-cost low-power droop-voltage-aware delay-fault-prevention designs for DVS caches.

Pei-Yuan Chou, I-Chen Wu, Jai-Wei Lin, Xuan-Yu Lin, Tien-Fu Chen, Tay-Jyi Lin, Jinn-Shyan Wang

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm² all-digital delay-locked loop in 65-nm CMOS.

Chun-Yuan Cheng, Jinn-Shyan Wang, Pei-Yuan Chou, Shiou-Ching Chen, Chi-Tien Sun, Yuan-Hua Chu, Tzu-Yi Yang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014