Philip Colangelo

According to our database1, Philip Colangelo authored at least 17 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2023
Exploring the Use of Dataflow Architectures for Graph Neural Network Workloads.
Proceedings of the High Performance Computing, 2023

2020
AutoML for Multilayer Perceptron and FPGA Co-design.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

Sparse Persistent GEMM Accelerator using OpenCL for Intel FPGAs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Automated Hardware and Neural Network Architecture co-design of FPGA accelerators using multi-objective Neural Architecture Search.
Proceedings of the 10th IEEE International Conference on Consumer Electronics, 2020

2019
Evolutionary Cell Aided Design for Neural Network Architectures.
CoRR, 2019

BFLOAT MLP Training Accelerator for FPGAs.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

Artificial Neural Network and Accelerator Co-design using Evolutionary Algorithms.
Proceedings of the 2019 IEEE High Performance Extreme Computing Conference, 2019

2018
Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs.
CoRR, 2018

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs: (Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017
Application of convolutional neural networks on Intel® Xeon® processor with integrated FPGA.
Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

Fine-Grained Acceleration of Binary Neural Networks Using Intel® Xeon® Processor with Integrated FPGA.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

2016
Document classification systems in heterogeneous computing environments.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

2015
SparkCL: A Unified Programming Framework for Accelerators on Heterogeneous Clusters.
CoRR, 2015

Aparapi-UCores: A high level programming framework for unconventional cores.
Proceedings of the 2015 IEEE High Performance Extreme Computing Conference, 2015


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