Utku Aydonat

Orcid: 0000-0003-2510-5442

According to our database1, Utku Aydonat authored at least 10 papers between 2004 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Compute Substrate for Software 2.0.
IEEE Micro, 2021

2018
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017
Creating High Performance Applications with Intel's FPGA OpenCL™ SDK.
Proceedings of the 5th International Workshop on OpenCL, 2017

An OpenCL™ Deep Learning Accelerator on Arria 10.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2012
Relaxed Concurrency Control in Software Transactional Memory.
IEEE Trans. Parallel Distributed Syst., 2012

From opencl to high-performance hardware on FPGAS.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011
Parallelization of multimedia applications on the multi-level computing architecture.
J. Embed. Comput., 2011

2010
Hardware Support for Relaxed Concurrency Control in Transactional Memory.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

2004
A Multilevel Computing Architecture for Embedded Multimedia Applications.
IEEE Micro, 2004


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