Aravind Dasu

According to our database1, Aravind Dasu authored at least 35 papers between 2001 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
Specializing FGPU for Persistent Deep Learning.
ACM Trans. Reconfigurable Technol. Syst., 2021

FlexScore: Quantifying Flexibility.
IEEE Comput. Archit. Lett., 2021

DO-GPU: Domain Optimizable Soft GPUs.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

2020
FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019
IP Cores for Graph Kernels on FPGAs.
Proceedings of the 2019 IEEE High Performance Extreme Computing Conference, 2019

Automatic Compiler Based FPGA Accelerator for CNN Training.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018
A Faddeev Systolic Array for EKF-SLAM and its Arithmetic Data Representation Impact on FPGA.
J. Signal Process. Syst., 2018

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2014
A power efficient reconfigurable system-in-stack: 3D integration of accelerators, FPGAs, and DRAM.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

2011
Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010).
Int. J. Reconfigurable Comput., 2011

2010
Dynamically reconfigurable systolic array accelerators: A case study with extended Kalman filter and discrete wavelet transform algorithms.
IET Comput. Digit. Tech., 2010

Methodology to derive resource aware context adaptable architectures for FPGAs.
IET Comput. Digit. Tech., 2010

Self-configurable architecture for reusable systems with Accelerated Relocation Circuit (SCARS-ARC).
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Memory architecture template for Fast Block Matching algorithms on FPGAs.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Welcome message.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

2009
Analysis and Design of a Context Adaptable SAD/MSE Architecture.
Int. J. Reconfigurable Comput., 2009

Methodology to derive context adaptable architectures for FPGAs.
IET Comput. Digit. Tech., 2009

PRR-PRR Dynamic Relocation.
IEEE Comput. Archit. Lett., 2009

2008
Hardware/Software Co-designed Extended Kalman Filter on an FPGA.
Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

2007
Performance of a LU decomposition on a multi-FPGA system compared to a low power commodity microprocessor system.
Scalable Comput. Pract. Exp., 2007

A Reconfigurable Load Balancing Architecture for Molecular Dynamics.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

2006
Memory support design for LU decomposition on the starbridge hyper-computer.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

2005
High Level - Application Analysis Techniques & Architectures - To Explore Design possibilities for Reduced Reconfiguration Area Overheads in FPGAs executing Compute Intensive Applications.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

A Fast and Efficient FPGA-Based Implementation for Solving a System of Linear Interval Equations.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

2004
A wavelet-based sprite codec.
IEEE Trans. Circuits Syst. Video Technol., 2004

Task Scheduling of Control-Data Flow Graphs for Reconfigurable Architectures.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

Cluster Extraction for Hybrid FPGA Architecture in Computation Intensive Applications.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004

2003
An Analysis Tool Set for Reconfigurable Media Processing.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, June 23, 2003

2002
A survey of media processing approaches.
IEEE Trans. Circuits Syst. Video Technol., 2002

Reconfigurable media processing.
Parallel Comput., 2002

Pattern Recognition Tool to Detect Reconfigurable Patterns in MPEG4 Video Processing.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

2001
Lifting kernel-based sprite codec.
Proceedings of the Visual Communications and Image Processing 2001, 2001


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