Philippe Royannez

According to our database, Philippe Royannez authored at least 8 papers between 1996 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2015

BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems.

Chao Wang, Jun Zhou, Roshan Weerasekera, Bin Zhao, Xin Liu, Philippe Royannez, Minkyu Je

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2012

Practical and efficient SOC verification flow by reusing IP testcase and testbench.

Zhaohui Hu, Arnaud Pierres, Shiqing Hu, Chen Fang, Philippe Royannez, Eng Pek See, Yean Ling Hoon

Proceedings of the International SoC Design Conference, 2012

2010

SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors.

Gordon Gammie, Alice Wang, Hugh Mair, Rolf Lagerquist, Minh Chau, Philippe Royannez, Sumanth Gururajarao, Uming Ko

Proc. IEEE, 2010

2008

A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques.

Gordon Gammie, Alice Wang, Minh Chau, Sumanth Gururajarao, Robert Pitts, Fabien Jumel, Stacey Engel, Philippe Royannez, Rolf Lagerquist, Hugh Mair, Jeff Vaccani, Greg Baldwin, Keerthi Heragu, Rituparna Mandal, Michael Clinton, Don Arden, Uming Ko

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

TD: Proximity Data and Power Transmission.

Chris Van Hoof, Philippe Royannez

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Solutions for logic and processor core design at the 45nm technology node & and below.

Philippe Royannez, Hugh Mair, Michael Clinton, Uming Ko

Proceedings of the 14th IEEE International Conference on Electronics, 2007

2005

A design platform for 90-nm leakage reduction techniques.

Philippe Royannez, Hugh Mair, Franck Dahan, Mike Wagner, Mark Streeter, Laurent Bouetel, Joel Blasquez, H. Clasen, G. Semino, Julie Dong, D. Scott, B. Pitts, Claudine Raibaut, Uming Ko

Proceedings of the 42nd Design Automation Conference, 2005

1996

A 1.0ns 64-bits GaAs Adder using Quad tree algorithm.

Philippe Royannez, Amara Amara

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996