Amara Amara

According to our database1, Amara Amara authored at least 48 papers between 1996 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
ICTs as catalysts in child protection programmes: current landscape in South Asia & a concept to inform future use.
Proceedings of the Tenth International Conference on Information and Communication Technologies and Development, 2019

Peer Networking and Capacity Building for Child Protection Professionals - Lessons from "ChildHub".
Proceedings of the Information and Communication Technologies for Development. Strengthening Southern-Driven Cooperation as a Catalyst for ICT4D, 2019

2017
Tunnel FET based ultra-low-leakage compact 2T1C SRAM.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

1.56GHz/0.9V energy-efficient reconfigurable CAM/SRAM using 6T-CMOS bitcell.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

Tunnel FET based refresh-free-DRAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Symbolic Fusion: A Novel Decision Support Algorithm for Sleep Staging Application.
EAI Endorsed Trans. Pervasive Health Technol., 2016

0.5-V Sub-ns Open-BL SRAM Array with Mid-Point-Sensing Multi-Power-Supply 5T Cell.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

TFET NDR skewed inverter based sensing method.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

0.5-V 50-mV-swing 1.2-GHz 28-nm-FD-SOI 32-bit dynamic bus architecture with dummy bus.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Ultra-Low-Power compact TFET Flip-Flop design for high-performance low-voltage applications.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

A cost-effective approach for ubiquitous broadband access based on hybrid PLC-VLC system.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Ultra-compact SRAM design using TFETs for low power low voltage applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Uplink wireless transmission overview in bi-directional VLC systems.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

16Kb hybrid TFET/CMOS reconfigurable CAM/SRAM array based on 9T-TFET bitcell.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

Personalized sleep staging system using evolutionary algorithm and symbolic fusion.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Cross entropy-based automatic thresholds setting-up method for sleep staging system.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

2015
Energy efficiency optimization for digital applications in 28nm UTBB FDSOI technology.
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

Sub-picowatt retention mode TFET memory for CMOS sensor processing nodes.
Proceedings of the 6th International Workshop on Advances in Sensors and Interfaces, 2015

0.5-V sub-ns open-BL SRAM array with mid-point-sensing multi-power 5T cell.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Ultra-low leakage sub-32nm TFET/CMOS hybrid 32kb pseudo DualPort scratchpad with GHz speed for embedded applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2013
CMOS SRAM scaling limits under optimum stability constraints.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Default connection in multi-electrode leads for cardiac pacemakers.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Bipolar ReRAM Based non-volatile flip-flops for low-power architectures.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

A 32nm tunnel FET SRAM for ultra low leakage.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
An Ultra-Low Power MAC Protocol for In-body Medical Implant Networks.
Proceedings of the Wireless Mobile Communication and Healthcare, 2011

Multi-electrode system for pacemaker applications.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Design of an ultra low power MAC for a heterogeneous in-body sensor network.
Proceedings of the 6th International Conference on Body Area Networks, 2011

2010
An On-Chip Multi-Mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-Power Domain SoC Using a 65-nm Standard CMOS Logic Process.
J. Low Power Electron., 2010

32nm and beyond Multi-VT Ultra-Thin Body and BOX FDSOI: From device to circuit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

An Innovative 6T Hybrid SRAM Cell in sub-32 nm Double-Gate MOS Technology.
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

2009
SRAM Voltage and Current Sense Amplifiers in sub-32nm Double-gate CMOS Insensitive to Process Variations and Transistor Mismatch.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
A novel 4T asymmetric single-ended SRAM cell in sub-32 nm double gate technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

An innovative sub-32nm SRAM voltage sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2007
A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
FPGA vs. ASIC for low power applications.
Microelectron. J., 2006

A Non-Volatile Multi-Level Memory Cell Using Molecular-Gated Nanowire Transistors.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Contribution of Custom Instructions on SoPC for iris recognition application.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Ultra low voltage design considerations of SOI SRAM memory cells.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Iris identification and robustness evaluation of a wavelet packets based algorithm.
Proceedings of the 2005 International Conference on Image Processing, 2005

2004
Modeling subthreshold SOI logic for static timing analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Systems-on-chip for telecommunications.
Ann. des Télécommunications, 2004

IRIS features extraction using wavelet packets.
Proceedings of the 2004 International Conference on Image Processing, 2004

2003
An SOI 4 transistors self-refresh ultra-low-voltage memory cell.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2001
Static power consumption management in CMOS memories.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1996
A 1.0ns 64-bits GaAs Adder using Quad tree algorithm.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996


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