Abdoulaye Gamatié

According to our database1, Abdoulaye Gamatié authored at least 73 papers between 2003 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
Other 

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Bibliography

2018
Exploration of a scalable and power-efficient asynchronous Network-on-Chip with dynamic resource allocation.
Microprocessors and Microsystems - Embedded Hardware Design, 2018

Energy-Efficient Memory Mappings based on Partial WCET Analysis and Multi-Retention Time STT-RAM.
Proceedings of the 26th International Conference on Real-Time Networks and Systems, 2018

A Compiler-Centric Infra-Structure for Whole-Board Energy Measurement on Heterogeneous Android Systems.
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018

Evaluation of Heterogeneous Multicore Cluster Architectures Designed for Mobile Computing.
Proceedings of the 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2018

Compile-Time Silent-Store Elimination for Energy Efficiency: an Analytic Evaluation for Non-Volatile Cache Memory.
Proceedings of the RAPIDO 2018 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2018

Using multifunctional standardized stack as universal spintronic technology for IoT.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Improving the Performance of STT-MRAM LLC Through Enhanced Cache Replacement Policy.
Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018

2017
ElasticSimMATE: A fast and accurate gem5 trace-driven simulator for multicore systems.
Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017

Distributed and Dynamic Shared-Buffer Router for High-Performance Interconnect.
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, 2017

Roundabout: A Network-on-Chip router with adaptive buffer sharing.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Scalable and Power-Efficient Implementation of an Asynchronous Router with Buffer Sharing.
Proceedings of the Euromicro Conference on Digital System Design, 2017

Embedded systems to high performance computing using STT-MRAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Model-Based Design of Correct Controllers for Dynamically Reconfigurable Architectures.
ACM Trans. Embedded Comput. Syst., 2016

Efficient Embedded Software Migration towards Clusterized Distributed-Memory Architectures.
IEEE Trans. Computers, 2016

Non-Volatile Processor Based on MRAM for Ultra-Low-Power IoT Devices.
JETC, 2016

Exploring MRAM Technologies for Energy Efficient Systems-On-Chip.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

A Workflow for Fast Evaluation of Mapping Heuristics Targeting Cloud Infrastructures.
CoRR, 2016

Speed and accuracy dilemma in NoC simulation: What about memory impact?
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

Loop optimization in presence of STT-MRAM caches: A study of performance-energy tradeoffs.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Performance Prediction of Application Mapping in Manycore Systems with Artificial Neural Networks.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Full-System Simulation of big.LITTLE Multicore Architecture for Performance and Energy Exploration.
Proceedings of the 10th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2016

Design space exploration for complex automotive applications: an engine control system case study.
Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation, 2016

2015
High-level design space exploration for adaptive applications on multiprocessor systems-on-chip.
Journal of Systems Architecture - Embedded Systems Design, 2015

Progressive and explicit refinement of scheduling for multidimensional data-flow applications using UML MARTE.
Design Autom. for Emb. Sys., 2015

Emerging Non-volatile Memory Technologies Exploration Flow for Processor Architecture.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

On the Performance Exploration of 3D NoCs with Resistive-Open TSVs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Design Exploration for next Generation High-Performance Manycore On-chip Systems: Application to big.LITTLE Architectures.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Discrete Control-Based Design of Adaptive and Autonomic Computing Systems.
Proceedings of the Distributed Computing and Internet Technology, 2015

Potential applications based on NVM emerging technologies.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A trace-driven approach for fast and accurate simulation of manycore architectures.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Adaptivity in high-performance embedded systems: a reactive control model for reliable and flexible design.
Knowledge Eng. Review, 2014

Performance exploration of partially connected 3D NoCs under manufacturing variability.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

2013
Special section on modeling of reactive systems.
Discrete Event Dynamic Systems, 2013

Autonomic Management of Dynamically Partially Reconfigurable FPGA Architectures Using Discrete Control.
Proceedings of the 10th International Conference on Autonomic Computing, 2013

2012
Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: Advantages, limitations and alternatives.
Journal of Systems Architecture - Embedded Systems Design, 2012

Abstract Clock-Based Design of a JPEG Encoder.
Embedded Systems Letters, 2012

Progressive and explicit refinement of scheduling for multidimensional data-flow applications using uml marte.
Design Autom. for Emb. Sys., 2012

CLASSY: a clock analysis system for rapid prototyping of embedded applications on MPSoCs.
Proceedings of the Workshop on Software and Compilers for Embedded Systems, 2012

Design space exploration in application-specific hardware synthesis for multiple communicating nested loops.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Abstract Clocks for the DSE of Data-Intensive Applications on MPSoCs.
Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012

Transformation-Based Exploration of Data Parallel Architecture for Customizable Hardware: A JPEG Encoder Case Study.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Design of streaming applications on MPSoCs using abstract clocks.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Design and Analysis for Multi-Clock and Data-Intensive Applications on Multiprocessor Systems-on-Chip.
, 2012

2011
Modélisation UML/MARTE de SoC et analyse temporelle basée sur l'approche synchrone. Vers l'exploration à haut niveau de l'architecture.
Technique et Science Informatiques, 2011

A Model-Driven Design Framework for Massively Parallel Embedded Systems.
ACM Trans. Embedded Comput. Syst., 2011

SMT based false causal loop detection during code synthesis from Polychronous specifications.
Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011

Static analysis of synchronous programs in signal for efficient design of multi-clocked embedded systems.
Proceedings of the ACM SIGPLAN/SIGBED 2011 conference on Languages, 2011

2010
The Signal Synchronous Multiclock Approach to the Design of Distributed Embedded Systems.
IEEE Trans. Parallel Distrib. Syst., 2010

Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation.
IJES, 2010

Operational Semantics of the Marte Repetitive Structure Modeling Concepts for Data-Parallel Applications Design.
Proceedings of the Ninth International Symposium on Parallel and Distributed Computing, 2010

Architecture Exploration for Efficient Data Transfer and Storage in Data-Parallel Applications.
Proceedings of the Euro-Par 2010 - Parallel Processing, 16th International Euro-Par Conference, Ischia, Italy, August 31, 2010

Designing Embedded Systems with the SIGNAL Programming Language - Synchronous, Reactive Specification.
Springer, ISBN: 978-1-4419-0940-4, 2010

2009
Model-Driven Engineering and Formal Validation of High-Performance Embedded Systems.
Scalable Computing: Practice and Experience, 2009

A metamodel for the design of polychronous systems.
J. Log. Algebr. Program., 2009

A Case Study on Controller Synthesis for Data-Intensive Embedded Systems.
Proceedings of the International Conference on Embedded Software and Systems, 2009

Model-Driven Design of Embedded Multimedia Applications on SoCs.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008
Safe design of high-performance embedded systems in an MDE framework.
ISSE, 2008

Synchronous Modeling and Analysis of Data Intensive Applications.
EURASIP J. Emb. Sys., 2008

Modeling and Formal Validation of High-Performance Embedded Systems.
Proceedings of the 7th International Symposium on Parallel and Distributed Computing (ISPDC 2008), 2008

MARTE-based Design of a Multimedia Application and Formal Analysis.
Proceedings of the Forum on specification and Design Languages, 2008

An Interval-Based Solution for Static Analysis in the SIGNAL Language.
Proceedings of the 15th Annual IEEE International Conference and Workshop on Engineering of Computer Based Systems (ECBS 2008), 31 March, 2008

2007
Polychronous design of embedded real-time applications.
ACM Trans. Softw. Eng. Methodol., 2007

Model Transformations from a Data Parallel Formalism towards Synchronous Languages.
Proceedings of the Forum on specification and Design Languages, 2007

2006
Synchronous design of avionic applications based on model refinement.
J. Embedded Computing, 2006

A Modeling Paradigm for Integrated Modular Avionics Design.
Proceedings of the 32nd EUROMICRO Conference on Software Engineering and Advanced Applications (EUROMICRO-SEAA 2006), August 29, 2006

Polychronous mode automata.
Proceedings of the 6th ACM & IEEE International conference on Embedded software, 2006

2004
Modélisation polychrone et évaluation de systèmes temps réel. (Polychronous modeling and evaluation of real-time systems).
PhD thesis, 2004

Modeling of Avionics Applications and Performance Evaluation Techniques Using the Synchronous Language SIGNAL.
Electr. Notes Theor. Comput. Sci., 2004

A Behavioral Type Inference System for Compositional System-on-Chip Design.
Proceedings of the 4th International Conference on Application of Concurrency to System Design (ACSD 2004), 2004

2003
Synchronous Modeling of Avionics Applications using the SIGNAL Languag.
Proceedings of the 9th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2003), 2003

Hard Real-Time Implementation of Embedded Software in JAVA.
Proceedings of the Scientific Engineering of Distributed Java Applications, 2003

The SIGNAL Approach to the Design of System Architectures.
Proceedings of the 10th IEEE International Conference on Engineering of Computer-Based Systems (ECBS 2003), 2003


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