Pietro Nannipieri
Orcid: 0000-0002-2538-5440
According to our database1,
Pietro Nannipieri authored at least 38 papers
between 2017 and 2026.
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Bibliography
2026
A Tightly-Coupled RISC-V ISA Extension to Speed-Up a Code-Based Post Quantum Digital Signature Scheme.
IEEE Access, 2026
2025
IEEE Trans. Very Large Scale Integr. Syst., December, 2025
Hardware Design of an Advanced-Feature Cryptographic Tile Within the European Processor Initiative.
IEEE Trans. Computers, March, 2025
Efficient Coarse-Grained Reconfigurable Array architecture for machine learning applications in space using DARE65T library platform.
Microprocess. Microsystems, 2025
FPG-AI RNN: A Technology-Agnostic Framework for the Automatic Acceleration of LSTM/GRU-Based Models on FPGAs.
IEEE Access, 2025
IEEE Access, 2025
RADSAFiE: A Netlist-Level Fault Injection User Interface Application for FPGA-Based Digital Systems.
IEEE Access, 2025
A Robust and Portable All-Digital TRNG Circuit for Extending the Instruction Set Architecture of RISC-V Processors.
IEEE Access, 2025
UVM-Based Verification of a Configurable Data Flow-Control IP Core for FPGA CNN Accelerators.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2025
2024
Integration of Twin Models in UVM Verification IPs for Space Telecommunication Systems.
IEEE Access, 2024
Design and Implementation of a Configurable Fully Compliant DVB-S2 LDPC Encoder for High Data-Rate Downlink Payload.
IEEE Access, 2024
Enhancing a Soft GPU IP Reliability Against SEUs in Space: Modelling Approach and Criticality Analysis on a Radiation-Tolerant FPGA.
Proceedings of the 8th International Conference on System Reliability and Safety, 2024
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024
Flexible Precision Vector Extension for Energy Efficient Coarse-Grained Reconfigurable Array AI-Engine.
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024
2023
SpaceART SpaceWire Sniffer for Link Monitoring: A Complete Communication Analysis in a Time-Constrained Test Scenario.
Sensors, February, 2023
Design and Implementation of a DVB-S2 Reconfigurable Datapath BCH Encoder for High Data-Rate Payload Data Telemetry.
IEEE Access, 2023
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023
Cycle-Accurate Verification of the Cryptographic Co-Processor for the European Processor Initiative.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023
2022
VLSI Design of Advanced-Features AES Cryptoprocessor in the Framework of the European Processor Initiative.
IEEE Trans. Very Large Scale Integr. Syst., 2022
Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source.
Entropy, 2022
Architectural Implications for Inference of Graph Neural Networks on CGRA-based Accelerators.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
2021
SHA2 and SHA-3 accelerator design in a 7 nm technology within the European Processor Initiative.
Microprocess. Microsystems, November, 2021
A RISC-V Post Quantum Cryptography Instruction Set Extension for Number Theoretic Transform to Speed-Up CRYSTALS Algorithms.
IEEE Access, 2021
A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design of System-on-Chip exploiting RISC-V Architecture.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021
CRFlex: A Flexible and Configurable Cryptographic Hardware Accelerator for AES Block Cipher Modes.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2021
2019
Clustering Algorithm for a Spaceborne Lightning Imager: Design, Trade-Off, and FPGA Implementation.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2019
A Complete EGSE Solution for the SpaceWire and SpaceFibre Protocol Based on the PXI Industry Standard.
Sensors, 2019
A Configurable Hardware Word Re-Ordering Block for Multi-Lane Communication Protocols: Design and Use Case.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
Exploiting LabViewFpga Socketed CLIP to Design and Implement Soft-Core Based Complex Digital Architectures on PXI FPGA Target Boards.
Proceedings of the 16th International Conference on Synthesis, 2019
AXI4LV: Design and Implementation of a Full-Speed AMBA AXI4-Burst DMA Interface for LabVIEW FPGA.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019
Integration of a SpaceFibre IP Core with the LEON3 Microprocessor Through an AMBA AHB Bus.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019
2018
A Novel Parallel 8B/10B Encoder: Architecture and Comparison with Classical Solution.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
A SpaceFibre multi lane codec System on a Chip: enabling technology for low cost satellite EGSE.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2018
2017
The U-PHOS experience within the ESA student REXUS/BEXUS programme: A real space hands-on opportunity.
Proceedings of the 2017 IEEE Global Engineering Education Conference, 2017