Plamen Asenov

According to our database1, Plamen Asenov authored at least 7 papers between 2011 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Exploring Power Savings of Gate-All-Around Cryogenic Technology.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2017
TCAD based Design-Technology Co-Optimisations in advanced technology nodes.
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

2016
Nanowire transistor solutions for 5nm and beyond.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

2015
Unified approach for simulation of statistical reliability in nanoscale CMOS transistors from devices to circuits.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2013
Evaluating the accuracy of SRAM margin simulation through large scale Monte-Carlo simulations with accurate compact models.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

2012
An advanced statistical compact model strategy for SRAM simulation at reduced VDD.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2011
Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis.
Proceedings of the Design, Automation and Test in Europe, 2011


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