Dave Reid

According to our database1, Dave Reid authored at least 12 papers between 1994 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
Unified approach for simulation of statistical reliability in nanoscale CMOS transistors from devices to circuits.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Statistical simulations of 6T-SRAM cell ageing using a reliability aware simulation flow.
Proceedings of the 45th European Solid State Device Research Conference, 2015

2014
Modelling RTN and BTI in nanoscale MOSFETs from device to circuit: A review.
Microelectron. Reliab., 2014

2013
SRAM device and cell co-design considerations in a 14nm SOI FinFET technology.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Evaluating the accuracy of SRAM margin simulation through large scale Monte-Carlo simulations with accurate compact models.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

Investigation of SRAM using BTI-aware statistical compact models.
Proceedings of the European Solid-State Device Research Conference, 2013

2012
An advanced statistical compact model strategy for SRAM simulation at reduced VDD.
Proceedings of the 2012 European Solid-State Device Research Conference, 2012

2011
The evolution of standard cell libraries for future technology nodes.
Genet. Program. Evolvable Mach., 2011

Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis.
Proceedings of the Design, Automation and Test in Europe, 2011

2009
Enabling Cutting-Edge Semiconductor Simulation through Grid Technology.
Proceedings of the Large-Scale Scientific Computing, 7th International Conference, 2009

2008
Statistical simulation of random dopant induced threshold voltage fluctuations for 35 nm channel length MOSFET.
Microelectron. Reliab., 2008

1994
Speed-Up of Scalable Iterative Linear Solvers Implemented on an Array of Transputers.
Parallel Comput., 1994


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