Steve B. Furber
Orcid: 0000-0002-6524-3367Affiliations:
- University of Manchester, School of Computer Science, UK
According to our database1,
Steve B. Furber
authored at least 216 papers
between 1987 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2005, "For contributions to the microarchitecture of embedded processor cores.".
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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Bibliography
2023
BitBrain and Sparse Binary Coincidence (SBC) memories: Fast, robust learning and inference for neuromorphic architectures.
Frontiers Neuroinformatics, March, 2023
NeuroBench: Advancing Neuromorphic Computing through Collaborative, Fair and Representative Benchmarking.
CoRR, 2023
CoRR, 2023
A High-Throughput Low-Latency Interface Board for SpiNNaker-in-the-loop Real-Time Systems.
Proceedings of the 2023 International Conference on Neuromorphic Systems, 2023
2022
Neuromorph. Comput. Eng., 2022
Neuromorph. Comput. Eng., 2022
Proceedings of the Neural Information Processing - 29th International Conference, 2022
Unsupervised STDP-based Radioisotope Identification Using Spiking Neural Networks Implemented on SpiNNaker.
Proceedings of the 8th International Conference on Event-Based Control, 2022
2021
Comparing Loihi with a SpiNNaker 2 prototype on low-latency keyword spotting and adaptive robotic control.
Neuromorph. Comput. Eng., 2021
The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing.
CoRR, 2021
An FPGA Implementation of Convolutional Spiking Neural Networks for Radioisotope Identification.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Towards Biologically-Plausible Neuron Models and Firing Rates in High-Performance Deep Spiking Neural Networks.
Proceedings of the ICONS 2021: International Conference on Neuromorphic Systems 2021, 2021
2020
Low-Power Low-Latency Keyword Spotting and Adaptive Control with a SpiNNaker 2 Prototype and Comparison with Loihi.
CoRR, 2020
IEEE Access, 2020
IEEE Access, 2020
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Proceedings of the 6th International Conference on Event-Based Control, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Biomed. Circuits Syst., 2019
SpiNNaker 2: A 10 Million Core Processor System for Brain Simulation and Machine Learning.
CoRR, 2019
Stochastic rounding and reduced-precision fixed-point arithmetic for solving neural ODEs.
CoRR, 2019
SLAMBench 3.0: Systematic Automated Reproducible Evaluation of SLAM Systems for Robot Vision Challenges and Scene Understanding.
Proceedings of the International Conference on Robotics and Automation, 2019
2018
IEEE Trans. Neural Networks Learn. Syst., 2018
IEEE Trans. Multi Scale Comput. Syst., 2018
Parallel Distribution of an Inner Hair Cell and Auditory Nerve Model for Real-Time Application.
IEEE Trans. Biomed. Circuits Syst., 2018
IEEE Trans. Cogn. Dev. Syst., 2018
Visual attention and object naming in humanoid robots using a bio-inspired spiking neural network.
Robotics Auton. Syst., 2018
Navigating the Landscape for Real-Time Localization and Mapping for Robotics and Virtual and Augmented Reality.
Proc. IEEE, 2018
Navigating the Landscape for Real-time Localisation and Mapping for Robotics and Virtual and Augmented Reality.
CoRR, 2018
Performance Comparison of Time-Step-Driven versus Event-Driven Neural State Update Approaches in SpiNNaker.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Deep Spiking Neural Network model for time-variant signals classification: a real-time speech recognition approach.
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018
Proceedings of the 2018 IEEE International Conference on Robotics and Automation, 2018
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018
Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip.
Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018
2017
On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems.
IEEE Trans. Biomed. Circuits Syst., 2017
CoRR, 2017
IEEE Access, 2017
Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Live demonstration: Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Parallel distribution of an inner hair cell and auditory nerve model for real-time application.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017
2016
Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
CoRR, 2016
pyDVS: An extensible, real-time Dynamic Vision Sensor emulator using off-the-shelf hardware.
Proceedings of the 2016 IEEE Symposium Series on Computational Intelligence, 2016
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016
High performance computing on SpiNNaker neuromorphic platform: A case study for energy efficient image processing.
Proceedings of the 35th IEEE International Performance Computing and Communications Conference, 2016
Efficient SpiNNaker simulation of a heteroassociative memory using the Neural Engineering Framework.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
Proceedings of the Neural Information Processing - 23rd International Conference, 2016
2015
Proceedings of the Parallel Computing: On the Road to Exascale, 2015
Live demonstration: Handwritten digit recognition using spiking deep belief networks on SpiNNaker.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Real-time event-driven spiking neural network object recognition on the SpiNNaker platform.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Scalable energy-efficient, low-latency implementations of trained spiking Deep Belief Networks on SpiNNaker.
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015
Proceedings of the IEEE International Conference on Robotics and Automation, 2015
Proceedings of the Neural Information Processing - 22nd International Conference, 2015
Markov Chain Monte Carlo inference on graphical models using event-based processing on the SpiNNaker neuromorphic architecture.
Proceedings of the 49th Annual Conference on Information Sciences and Systems, 2015
2014
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014
Proceedings of the 2014 International Joint Conference on Neural Networks, 2014
Proceedings of the 2014 IEEE International Conference on Robotics and Automation, 2014
Proceedings of the Neural Information Processing - 21st International Conference, 2014
Proceedings of the Computing Frontiers Conference, CF'14, 2014
2013
SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture.
Parallel Comput., 2013
SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation.
IEEE J. Solid State Circuits, 2013
IET Comput. Digit. Tech., 2013
Proceedings of the Parallel Computing: Accelerating Computational Science and Engineering (CSE), 2013
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
Spike-based learning of transfer functions with the SpiNNaker neuromimetic simulator.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
Real-Time Interface Board for Closed-Loop Robotic Tasks on the SpiNNaker Neural Computing System.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2013, 2013
Live demonstration: Ethernet communication linking two large-scale neuromorphic systems.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
Proceedings of the 35th Annual Meeting of the Cognitive Science Society, 2013
Proceedings of the 35th Annual Meeting of the Cognitive Science Society, 2013
2012
Neural Networks, 2012
J. Parallel Distributed Comput., 2012
Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System.
Int. J. Parallel Program., 2012
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012
Proceedings of the 2012 International Joint Conference on Neural Networks (IJCNN), 2012
A Real-Time, Event-Driven Neuromorphic System for Goal-Directed Attentional Selection.
Proceedings of the Neural Information Processing - 19th International Conference, 2012
Analytical Assessment of the Suitability of Multicast Communications for the SpiNNaker Neuromimetic System.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the 34th Annual Meeting of the Cognitive Science Society, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
A hierachical configuration system for a massively parallel neural hardware platform.
Proceedings of the Computing Frontiers Conference, CF'12, 2012
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012
Large-Scale On-Chip Dynamic Programming Network Inferences Using Moderated Inter-core Communication.
Proceedings of the 12th International Conference on Application of Concurrency to System Design, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric.
Parallel Comput., 2011
Neural Networks, 2011
ACM J. Emerg. Technol. Comput. Syst., 2011
Proceedings of the Neural Nets WIRN11, 2011
Proceedings of the Applications, Tools and Techniques on the Road to Exascale Computing, Proceedings of the conference ParCo 2011, 31 August, 2011
Distributed configuration of massively-parallel simulation on SpiNNaker neuromorphic hardware.
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011
Representing and decoding rank order codes using polychronization in a network of spiking neurons.
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011
Proceedings of the Neural Information Processing - 18th International Conference, 2011
Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis.
Proceedings of the Design, Automation and Test in Europe, 2011
Biologically-inspired massively-parallel architectures - Computing beyond a million processors.
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 8th Conference on Computing Frontiers, 2011
Biologically-Inspired Massively-Parallel Architectures: A Reconfigurable Neural Modelling Platform.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011
2010
IEEE Trans. Neural Networks, 2010
Comput. J., 2010
Aust. J. Intell. Inf. Process. Syst., 2010
Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware.
Proceedings of the Ninth International Symposium on Parallel and Distributed Computing, 2010
The Leaky Integrate-and-Fire neuron: A platform for synaptic model exploration on the SpiNNaker chip.
Proceedings of the International Joint Conference on Neural Networks, 2010
Proceedings of the International Joint Conference on Neural Networks, 2010
Algorithm and software for simulation of spiking neural networks on the multi-chip SpiNNaker system.
Proceedings of the International Joint Conference on Neural Networks, 2010
Proceedings of the Neural Information Processing. Theory and Algorithms, 2010
Proceedings of the 7th Conference on Computing Frontiers, 2010
SpiNNaker: impact of traffic locality, causality and burstiness on the performance of the interconnection network.
Proceedings of the 7th Conference on Computing Frontiers, 2010
Efficient parallel implementation of multilayer backpropagation networks on SpiNNaker.
Proceedings of the 7th Conference on Computing Frontiers, 2010
Proceedings of the 7th Conference on Computing Frontiers, 2010
2009
A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect.
Fundam. Informaticae, 2009
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric.
Proceedings of the Eighth International Symposium on Parallel and Distributed Computing, 2009
Proceedings of the International Joint Conference on Neural Networks, 2009
Proceedings of the International Joint Conference on Neural Networks, 2009
Proceedings of the International Joint Conference on Neural Networks, 2009
Proceedings of the 23rd international conference on Supercomputing, 2009
Proceedings of the Neural Information Processing, 16th International Conference, 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009
Biologically-Inspired Massively-Parallel Architectures - Computing Beyond a Million Processors.
Proceedings of the Ninth International Conference on Application of Concurrency to System Design, 2009
2008
Proceedings of the Computational Intelligence: A Compendium, 2008
Comput. J., 2008
An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008
Proceedings of the International Joint Conference on Neural Networks, 2008
Proceedings of the International Joint Conference on Neural Networks, 2008
Proceedings of the International Joint Conference on Neural Networks, 2008
Proceedings of the Advances in Neuro-Information Processing, 15th International Conference, 2008
Proceedings of the Advances in Neuro-Information Processing, 15th International Conference, 2008
Proceedings of the 8th International Conference on Application of Concurrency to System Design (ACSD 2008), 2008
2007
IEEE Trans. Neural Networks, 2007
IEEE Des. Test Comput., 2007
Proceedings of the Data Mining, 2007
2006
An associative memory for the on-line recognition and prediction of temporal sequences
CoRR, 2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 11th European Test Symposium, 2006
2005
A System for Transmitting a Coherent Burst of Activity Through a Network of Spiking Neurons.
Proceedings of the Neural Nets, 16th Italian Workshop on Neural Nets, 2005
Proceedings of the Integrated Circuit and System Design, 2005
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Proceedings of the 2005 International Symposium on System-on-Chip, 2005
A Spiking Neural Sparse Distributed Memory Implementation for Learning and Predicting Temporal Sequences.
Proceedings of the Artificial Neural Networks: Biological Inspirations, 2005
2004
IEEE Trans. Computers, 2004
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
Proceedings of the Integrated Circuit and System Design, 2004
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Proceedings of the 2004 Design, 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003
2002
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002
2001
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001
2000
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000
1999
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999
1998
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Modelling and Simulation of Asynchronous Systems Using the LARD Hardware Description Language.
Proceedings of the 12<sup>th</sup> European Simulation Multiconference - Simulation, 1998
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998
1997
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997
1996
IEEE Trans. Very Large Scale Integr. Syst., 1996
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996
1995
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995
1994
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994
Proceedings of the Spring COMPCON 94, Digest of Papers, San Francisco, California, USA, February 28, 1994
1993
A micropipelined ARM.
Proceedings of the VLSI 93, 1993
1992
RISC architectures : Heudin, J C and Panetto, C Chapman & Hall, London, UK (1992) ISBN 0 412 45340 1, £19.95, pp 261.
Microprocess. Microsystems, 1992
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992
1990
1987
RISC architecture: D Tabak Research Studies Press, Letchworth, UK (1987) £19.95 pp 175.
Microprocess. Microsystems, 1987