Pooria M. Yaghini

Orcid: 0000-0002-0352-0197

According to our database1, Pooria M. Yaghini authored at least 20 papers between 2009 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Near Volatile and Non-Volatile Memory Processing in 3D Systems.
IEEE Trans. Emerg. Top. Comput., 2022

2021
Application Characterization for Near Memory Processing.
Proceedings of the 29th Euromicro International Conference on Parallel, 2021

2019
SpecLock: Speculative Lock Forwarding.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

2018
A Compositional Approach for Verifying Protocols Running on On-Chip Networks.
IEEE Trans. Computers, 2018

2017
Deadlock Verification of Cache Coherence Protocols and Communication Fabrics.
IEEE Trans. Computers, 2017

2016
Capacitive and Inductive TSV-to-TSV Resilient Approaches for 3D ICs.
IEEE Trans. Computers, 2016

ADVOCAT: Automated deadlock verification for on-chip cache coherence and interconnects.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Coupling Mitigation in 3-D Multiple-Stacked Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Analytical Fault Tolerance Assessment and Metrics for TSV-Based 3D Network-on-Chip.
IEEE Trans. Computers, 2015

Analytical Reliability Analysis of 3D NoC under TSV Failure.
ACM J. Emerg. Technol. Comput. Syst., 2015

On the design of hybrid routing mechanism for mesh-based network-on-chip.
Integr., 2015

Capacitive Coupling Mitigation for TSV-based 3D ICs.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Accurate System-level TSV-to-TSV Capacitive Coupling Fault Model for 3D-NoC.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

2014
A GALS Router for Asynchronous Network-on-Chip.
Proceedings of the 2nd International Workshop on Many-core Embedded Systems, 2014

TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-Chip.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2011
Investigation of transient fault effects in synchronous and asynchronous Network on Chip router.
J. Syst. Archit., 2011

2010
Test Documentation Tools and CBR Reduce the Cost of Testing.
Proceedings of the 2010 International Conference on Software Engineering Research & Practice, 2010

Investigation of Transient Fault Effects in an Asynchronous NoC Router.
Proceedings of the 18th Euromicro Conference on Parallel, 2010

2009
Fault tolerance assessment of PIC microcontroller based on fault injection.
Proceedings of the 10th Latin American Test Workshop, 2009

Fault injection-based evaluation of a synchronous NoC router.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009


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