Prab Varma

According to our database1, Prab Varma authored at least 21 papers between 1984 and 2016.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2011, "For contributions to system-on-chip test technology".

Timeline

Legend:

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Links

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Bibliography

2016
Welcome Message.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

2012
Current and Future Directions in Automatic Test Pattern Generation for Power Delivery Network Validation.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2004
Verification evolution or industrial revolution?
IEEE Des. Test Comput., 2004

2003
Design Verification Problems: Test To The Rescue?
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2001
ATPG for Design Errors-Is It Possible?
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

2000
Test Cycle Count Reduction in a Parallel Scan BIST Environment.
J. Electron. Test., 2000

1998
A structured test re-use methodology for core-based system chips.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

System chip test: are we there yet?
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

System Chip Test Challenges, Are There Solutions Today? (Panel).
Proceedings of the 35th Conference on Design Automation, 1998

1997
Test Compaction in a Parallel Access Scan Environment.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996
Delay Fault Testing: How Robust are Our Models?
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

A Unifying Methodology for Intellectual Property and Custom Logic Testing.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1995
Optimizing Product Profitability - The Test Way.
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

1994
The economics of scan-path design for testability.
J. Electron. Test., 1994

On Path-Delay Testing in a Standard Scan Environment.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1993
Delay Testing Using a Matrix of Accessible Storage.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

Scan DFT: Why More Can Cost Less.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

1992
On test generation for path delay faults in ASICs.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

1990
TDRC-a symbolic simulation based design for testability rules checker.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1987
A Fast Signature Simulation Tool for Built-In Self-Testing Circuits.
Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1984
An Analysis of the Economics of Self Test.
Proceedings of the Proceedings International Test Conference 1984, 1984


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