According to our database1, Sandeep Bhatia authored at least 18 papers between 1993 and 2019.
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Proceedings of the 2019 International Conference on Management of Data, 2019
IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers.
Proceedings of the 23rd IEEE European Test Symposium, 2018
In-silico search of virus-specific host microRNAs regulating avian influenza virus NS1 expression.
Theory Biosci., 2015
Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression.
IEICE Trans. Inf. Syst., 2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
A Partitioning Based Physical Scan Chain Allocation Algorithm that Minimizes Voltage Domain Crossings.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 17th IEEE Asian Test Symposium, 2008
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits.
IEEE Trans. Very Large Scale Integr. Syst., 1998
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997
Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996
Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional Branches.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
Proceedings of the Sixth International Conference on VLSI Design, 1993
Synthesis of Sequential Circuits for Easy Testability Through Performance-Oriented Parallel Partial Scan.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993