Sandeep Bhatia

According to our database1, Sandeep Bhatia authored at least 18 papers between 1993 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Data Platform for Machine Learning.
Proceedings of the 2019 International Conference on Management of Data, 2019

IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers.
Proceedings of the 23rd IEEE European Test Symposium, 2018

In-silico search of virus-specific host microRNAs regulating avian influenza virus NS1 expression.
Theory Biosci., 2015

Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression.
IEICE Trans. Inf. Syst., 2010

Low power compression architecture.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

CTL and Its Usage in the EDA Industry.
IEEE Des. Test Comput., 2009

A Partitioning Based Physical Scan Chain Allocation Algorithm that Minimizes Voltage Domain Crossings.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Optimizing Test Data Volume Using Hybrid Compression.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

Test Compaction by Using Linear-Matrix Driven Scan Chains.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Integration of hierarchical test generation with behavioral synthesis of controller and data path circuits.
IEEE Trans. Very Large Scale Integr. Syst., 1998

A structured test re-use methodology for core-based system chips.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Test Compaction in a Parallel Access Scan Environment.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

A Unifying Methodology for Intellectual Property and Custom Logic Testing.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional Branches.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Genesis: A Behavioral Synthesis System for Hierarchical Testability.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Synthesis of Sequential Circuits for Robust Path Delay Fault Testability.
Proceedings of the Sixth International Conference on VLSI Design, 1993

Synthesis of Sequential Circuits for Easy Testability Through Performance-Oriented Parallel Partial Scan.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993