Pramod Kolar

According to our database, Pramod Kolar authored at least 8 papers between 2007 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

A methodology for yield-specific leakage estimation in memory.

Subho Chatterjee, Pramod Kolar, Wei Jian Chan, Jae Y. Ko, Gunjan H. Pandya

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2011

A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation.

Pramod Kolar, Eric Karl, Uddalak Bhattacharya, Fatih Hamzaoglu, Henry Nho, Yong-Gee Ng, Yih Wang, Kevin Zhang

IEEE J. Solid State Circuits, 2011

Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design.

Fatih Hamzaoglu, Yih Wang, Pramod Kolar, Liqiong Wei, Yong-Gee Ng, Uddalak Bhattacharya, Kevin Zhang

IEEE Des. Test Comput., 2011

2010

A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management.

Yih Wang, Uddalak Bhattacharya, Fatih Hamzaoglu, Pramod Kolar, Yong-Gee Ng, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr

IEEE J. Solid State Circuits, 2010

A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation.

Hyunwoo Nho, Pramod Kolar, Fatih Hamzaoglu, Yih Wang, Eric Karl, Yong-Gee Ng, Uddalak Bhattacharya, Kevin Zhang

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management.

Yih Wang, Uddalak Bhattacharya, Fatih Hamzaoglu, Pramod Kolar, Yong-Gee Ng, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications.

Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr

IEEE J. Solid State Circuits, 2008

2007

A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications.

Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Yih Zhang, Kevin Zhang, Mark Bohr

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007