Chia-Hong Jan
According to our database1,
Chia-Hong Jan
authored at least 6 papers
between 2007 and 2018.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2017, "For leadership in developing low power logic technologies for System-on-Chip".
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2018
Proceedings of the 2018 International Symposium on VLSI Design, 2018
2015
A 14 nm SoC platform technology featuring 2<sup>nd</sup> generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um<sup>2</sup> SRAM cells, optimized for low power, high performance and high density SoC products.
Proceedings of the Symposium on VLSI Circuits, 2015
2013
IEEE J. Solid State Circuits, 2013
2012
32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2008
A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications.
IEEE J. Solid State Circuits, 2008
2007
A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007