Pranay Prabhat

Orcid: 0000-0003-3495-0525

According to our database1, Pranay Prabhat authored at least 14 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2023
Pragmatic Memory-System Support for Intermittent Computing Using Emerging Nonvolatile Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

2021
A Supply Voltage Control Method for Performance Guaranteed Ultra-Low-Power Microcontroller.
IEEE J. Solid State Circuits, 2021

A Compact Model for Scalable MTJ Simulation.
CoRR, 2021

A Fokker-Planck Solver to Model MTJ Stochasticity.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

2020
27.2 M0N0: A Performance-Regulated 0.8-to-38MHz DVFS ARM Cortex-M33 SIMD MCU with 10nW Sleep Power.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS.
IEEE J. Solid State Circuits, 2019

A 65nm switched source line sub-threshold ROM using data encoding, with 0.3V Vmin and 47fJ/b access energy.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

A 0.98-nW/kHz 33-kHz Fully Integrated Subthreshold-Region Operation RC Oscillator With Forward-Body-Biasing.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2018
A bulk 65nm Cortex-M0+ SoC with All-Digital Forward Body Bias for 4.3X Subthreshold Speedup.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
Evaluation and analysis of single-phase clock flip-flops for NTV applications.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Unconventional Layout Techniques for a High Performance, Low Variability Subthreshold Standard Cell Library.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016
A Subthreshold ARM Cortex-M0+ Subsystem in 65 nm CMOS for WSN Applications with 14 Power Domains, 10T SRAM, and Integrated Voltage Regulator.
IEEE J. Solid State Circuits, 2016

Design challenges for near and sub-threshold operation: A case study with an ARM Cortex-M0+ based WSN subsystem.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

2015
8.1 An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65nm CMOS for WSN applications.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015


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