Prashant Choudhary

According to our database1, Prashant Choudhary authored at least 6 papers between 2012 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2021
ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET.
IEEE J. Solid State Circuits, 2021

10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture.
IEEE J. Solid State Circuits, 2021

2020

6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2014
A 8.125-15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2012
A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012


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