Shankar Tangirala

According to our database, Shankar Tangirala authored at least 3 papers between 2020 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A 0.23pJ/b 24Gb/s Modular D2D Interface with Zero Wake Penalty Clock Gating in 3nm.

Ravi Shivnaraine, Charles Boecker, Eric Groen, Simon Li, Ping Lu, Socrates D. Vamvakos, Roxanne Vu, Chris Hanke, Shankar Tangirala, Wen Liu, Marina Salik, Kevin Bartholomew, Sushmitha Reddy, Alex Tessitore, Aws Shallal, Kalyan Nallaparaju, Jin Liang, Minhan Chen, Shaishav Desai

Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2021

ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET.

Haidang Lin, Charlie Boecker, Masum Hossain, Shankar Tangirala, Roxanne Vu, Socrates D. Vamvakos, Eric Groen, Simon Li, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Hossein Taghavi, Marcus van Ierssel, AdilHussain Maniyar, Adam Wodkowski, Kulwant Brar, Nhat Nguyen, Shaishav Desai

IEEE J. Solid State Circuits, 2021

2020

A 4×112 Gb/s ADC-DSP Based Multistandard Receiver in 7nm FinFET.

Haidang Lin, Charles Boecker, Masum Hossain, Shankar Tangirala, Roxanne Vu, Socrates D. Vamvakos, Eric Groen, Simon Li, Prashant Choudhary, Nanyan Wang, Masumi Shibata, Hossein Taghavi, Marcus van Ierssel, AdilHussain Maniyar, Adam Wodkowski, Nhat Nguyen, Shaishav Desai

Proceedings of the IEEE Symposium on VLSI Circuits, 2020