Prasun Ghosal

Proceedings of the NoCArc '21: Proceedings of the 14th International Workshop on Network on Chip Architectures, Virtual Event, Greece, October 18, 2021

A Hybrid Adaptive Strategy for Task Allocation and Scheduling for Multi-applications on NoC-based Multicore Systems with Resource Sharing.

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Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Application of Logical Sub-networking in Congestion-aware Deadlock-free SDmesh Routing.

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[DOI]

ACM Trans. Embed. Comput. Syst., 2020

A low latency energy efficient BFT based 3D NoC design with zone based routing strategy.

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[DOI]

J. Syst. Archit., 2020

A cube-tree hybrid NoC topology with 3D mirroring technique for load balancing.

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[DOI]

Proceedings of the NanoCoCoA@SenSys '20: Proceedings of the 1st ACM International Workshop on Nanoscale Computing, 2020

Switching at flit level: A Congestion Efficient Flow Control Strategy for Network-on-Chip.

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[DOI]

Proceedings of the 28th Euromicro International Conference on Parallel, 2020

Regulating Degree of Adaptiveness for Performance-Centric NoC Routing.

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Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

2019

Dynamic Task Mapping and Scheduling with Temperature-Awareness on Network-on-Chip based Multicore Systems.

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[DOI]

Suraj Paul

J. Syst. Archit., 2019

A permanent fault tolerant dynamic task allocation approach for Network-on-Chip based multicore systems.

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[DOI]

Suraj Paul

Munshi Mostafijur Rahaman

J. Syst. Archit., 2019

Latency, Throughput and Power Aware Adaptive NoC Routing on Orthogonal Convex Faulty Region.

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[DOI]

J. Circuits Syst. Comput., 2019

Addressing Out-of-order Issue of Congestion-aware Adaptive Routing in Subnet based NoC.

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[DOI]

Arnab Nath

Proceedings of the TENCON 2019, 2019

Virtual circuit switch based orderly delivery of packets in adaptive NoC routing.

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[DOI]

Proceedings of the 12th International Workshop on Network on Chip Architectures, 2019

2018

Power Analysis of an mRNA-Ribosome System.

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[DOI]

Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

A Dynamic Resource Allocation Strategy for NoC Based Multicore Systems with Permanent Faults.

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[DOI]

Suraj Paul

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Correlating Fatality Rate to Road Accidents in India: A Case Study Using Big Data.

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[DOI]

Subha Koley

Saket Srivastava

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

Three Tier Architecture for IoT Driven Health Monitoring System Using Raspberry Pi.

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[DOI]

Neel Kamal

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

2017

Minimal reversible circuit synthesis on a DNA computer.

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[DOI]

Nat. Comput., 2017

Guest editorial - Special issue on hardware assisted techniques for IoT and bigdata applications.

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[DOI]

Integr., 2017

Performing Mathematics Using DNA: Complex Number Arithmetic Using Sticker Model.

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[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

An IoT Enabled Real-Time Communication and Location Tracking System for Vehicular Emergency.

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[DOI]

Subha Koley

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

MSM: Performance Enhancing Area and Congestion Aware Network-on-Chip Architecture.

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[DOI]

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

Realizing All Logic Operations Using mRNA-Ribosome System as a Post Si Alternative.

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[DOI]

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

2016

Design of a High-Performance CDMA-Based Broadcast-Free Photonic Multi-Core Network on Chip.

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[DOI]

Soumyajit Poddar

ACM Trans. Embed. Comput. Syst., 2016

Computing in Ribosomes: Performing Boolean Logic Using mRNA-Ribosome System.

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[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

STA: A Highly Scalable Low Latency Butterfly Fat Tree Based 3D NoC Design.

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[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

A Provably Good Method to Generate Good DNA Sequences.

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[DOI]

Swapan Shakhari

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

Mathematics Using DNA: Performing GCD and LCM on a DNA Computer.

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[DOI]

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

Post CMOS Computing Beyond Si: DNA Computer as Future Alternative.

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[DOI]

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

Computing in Ribosomes: Implementing Sequential Circuits Using mRNA-Ribosome System.

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[DOI]

Munshi Mostafijur Rahaman

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

A Scalable Hierarchical Ring Based Wireless Network-on-Chip.

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[DOI]

Siddhartha Biswas

Proceedings of the 2016 International Conference on Information Technology, 2016

2015

FuzzRoute: A Thermally Efficient Congestion-Free Global Routing Method for Three-Dimensional Integrated Circuits.

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[DOI]

Debashri Roy

ACM Trans. Design Autom. Electr. Syst., 2015

Addressing Hardware Security Challenges in Internet of Things: Recent Trends and Possible Solutions.

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[DOI]

Subha Koley

Proceedings of the 2015 IEEE 12th Intl Conf on Ubiquitous Intelligence and Computing and 2015 IEEE 12th Intl Conf on Autonomic and Trusted Computing and 2015 IEEE 15th Intl Conf on Scalable Computing and Communications and Its Associated Workshops (UIC-ATC-ScalCom), 2015

Enterprise Application Security in Android Devices Using Short Messaging Service under Unified Communication Framework.

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[DOI]

Souvik Chowdhury

Adaptive CDMA based multicast method for photonic networks on chip.

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[DOI]

Soumyajit Poddar

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Implementing Data Structure Using DNA: An Alternative in Post CMOS Computing.

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[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Multicore ICs: Recent Trends in Developing Methodologies and Frameworks for Simulation.

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[DOI]

Soumyajit Poddar

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

Power Minimization of a Memristor-Based Wien Bridge Oscillator through a Simscape Framework.

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[DOI]

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

Generalized Optimum Reversible Circuit Synthesis: A Memetic Approach.

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[DOI]

Roshni Chakraborty

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

2014

An ABCD Parameter Based Modeling and Analysis of Crosstalk Induced Effects in Multiwalled Carbon Nanotube Bundle Interconnects.

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[DOI]

Manodipan Sahoo

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

FuzzRoute: A Method for Thermally Efficient Congestion Free Global Routing in 3D ICs.

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[DOI]

Debashri Roy

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Data Correlation Aware Serial Encoding for Low Switching Power On-Chip Communication.

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[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

A Low Latency Scalable 3D NoC Using BFT Topology with Table Based Uniform Routing.

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[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

A performance enhancing hybrid locally mesh globally star NoC topology.

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[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

A Highly Parameterizable Simulator for Performance Analysis of NoC Architectures.

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[DOI]

Dhiman Ghosh

Proceedings of the 2014 International Conference on Information Technology, 2014

2013

Reversible circuit synthesis using ACO and SA based Quine-McCluskey method.

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[DOI]

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

An Area and Power Efficient Dynamic TDMA Based Photonic Network on Chip.

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Proceedings of the 2013 International Symposium on Electronic System Design, 2013

A fuzzified approach towards global routing in VLSI layout design.

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[DOI]

Debashri Roy

Proceedings of the FUZZ-IEEE 2013, 2013

2012

Diametrical Mesh Of Tree (D2D-MoT) Architecture: A Novel Routing Solution For NoC

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[DOI]

Sankar Karmakar

CoRR, 2012

Speed Optimization In Unplanned Traffic Using Bio-Inspired Computing And Population Knowledge Base

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[DOI]

CoRR, 2012

A Photonic Network on Chip with CDMA Links.

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[DOI]

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Routing in NoC on Diametrical 2D Mesh Architecture.

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Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Design of an NoC with on-chip photonic interconnects using adaptive CDMA links.

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[DOI]

Proceedings of the IEEE 25th International SOC Conference, 2012

Efficient and Compact Electrical Modeling of Multi Walled Carbon Nanotube Interconnects.

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[DOI]

Manodipan Sahoo

Proceedings of the International Symposium on Electronic System Design, 2012

SD2D: A Novel Routing Architecture for Network-on-Chip.

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[DOI]

Proceedings of the International Symposium on Electronic System Design, 2012

Diametric Mesh of Tree (DiaMoT) Routing Framework for High Performance NoCs: A Hierarchical Approach.

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[DOI]

Sunita Choudhuri

Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

Honey Bee Based Vehicular Traffic Optimization and Management.

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[DOI]

Arijit Chakraborty

Sabyasachee Banerjee

Proceedings of Seventh International Conference on Bio-Inspired Computing: Theories and Applications (BIC-TA 2012), 2012

A New Class of Obstacle Aware Steiner Routing in 3D Integrated Circuits.

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[DOI]

Satrajit Das

Arindam Das

Proceedings of the Advances in Computing and Information Technology - Proceedings of the Second International Conference on Advances in Computing and Information Technology (ACITY) July 13-15, 2012, Chennai, India, 2012

Obstacle Aware RMST Generation Using Non-Manhattan Routing for 3D ICs.

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[DOI]

Arindam Das

Satrajit Das

A Novel Algorithm for Obstacle Aware RMST Construction during Routing in 3D ICs.

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[DOI]