Himanshu Thapliyal

According to our database1, Himanshu Thapliyal authored at least 136 papers between 2003 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
Smart Wristband-Based Stress Detection Framework for Older Adults With Cortisol as Stress Biomarker.
IEEE Trans. Consumer Electron., 2021

Quantum circuit designs of carry lookahead adder optimized for T-count T-depth and qubits.
Sustain. Comput. Informatics Syst., 2021

Novel Secure MTJ/CMOS Logic (SMCL) for Energy-Efficient and DPA-Resistant Design.
SN Comput. Sci., 2021

Consumer Technology-Based Solutions for COVID-19.
IEEE Consumer Electron. Mag., 2021

Consumer Technologies for Smart Cities to Smart Villages.
Proceedings of the IEEE International Conference on Consumer Electronics, 2021

2-SPGAL: 2-Phase Symmetric Pass Gate Adiabatic Logic for Energy-Efficient Secure Consumer IoT.
Proceedings of the IEEE International Conference on Consumer Electronics, 2021

2020
Quasi-Adiabatic SRAM Based Silicon Physical Unclonable Function.
SN Comput. Sci., 2020

Exploration of Solar Cell Materials for Developing Novel PUFs in Cyber-Physical Systems.
SN Comput. Sci., 2020

Design of Adiabatic Logic-Based Energy-Efficient and Reliable PUF for IoT Devices.
ACM J. Emerg. Technol. Comput. Syst., 2020

T-count and Qubit Optimized Quantum Circuit Designs of Carry Lookahead Adder.
CoRR, 2020

Machine Learning Based Solutions for Real-Time Stress Monitoring.
IEEE Consumer Electron. Mag., 2020

PPG Based Continuous Blood Pressure Monitoring Framework for Smart Home Environment.
Proceedings of the 6th IEEE World Forum on Internet of Things, 2020

2-Phase Energy-Efficient Secure Positive Feedback Adiabatic Logic for CPA-Resistant IoT Devices.
Proceedings of the 6th IEEE World Forum on Internet of Things, 2020

Low-Power and Energy-Efficient Full Adders With Approximate Adiabatic Logic for Edge Computing.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

A PUF Based CAN Security Framework.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Technology Innovations for Smart Cities and Smart Villages.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020

Smart Home Sensor Anomaly Detection Using Convolutional Autoencoder Neural Network.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020

Approximate Adder Circuits Using Clocked CMOS Adiabatic Logic (CCAL) for IoT Applications.
Proceedings of the 2020 IEEE International Conference on Consumer Electronics (ICCE), 2020

Validating Physiological Stress Detection Model Using Cortisol as Stress Bio Marker.
Proceedings of the 2020 IEEE International Conference on Consumer Electronics (ICCE), 2020

Harnessing Uncertainty in Photoresistor Sensor for True Random Number Generation in IoT Devices.
Proceedings of the 2020 IEEE International Conference on Consumer Electronics (ICCE), 2020

Special Session: Quantum Carry Lookahead Adders for NISQ and Quantum Image Processing.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Special Session: A Novel Low-Power and Energy-Efficient Adiabatic Logic-In-Memory Architecture Using CMOS/MTJ.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019
EE-SPFAL: A Novel Energy-Efficient Secure Positive Feedback Adiabatic Logic for DPA Resistant RFID and Smart Card.
IEEE Trans. Emerg. Top. Comput., 2019

Quantum Circuit Design of a T-count Optimized Integer Multiplier.
IEEE Trans. Computers, 2019

Use of Thermistor Temperature Sensors for Cyber-Physical System Security.
Sensors, 2019

Design of Quantum Computing Circuits.
IT Prof., 2019

Design of a Piezoelectric-Based Physically Unclonable Function for IoT Security.
IEEE Internet Things J., 2019

Quantum Computing Circuits and Devices.
IEEE Des. Test, 2019

Emerging Paradigms in Vehicular Cybersecurity.
IEEE Consumer Electron. Mag., 2019

Hardware Security Primitives for Vehicles.
IEEE Consumer Electron. Mag., 2019

Approximate Energy Recovery 4-2 Compressor for Low-Power Sub-GHz IoT Applications.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable Function.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Design of Quantum Circuits for Cryptanalysis and Image Processing Applications.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Solving Energy and Cybersecurity Constraints in IoT Devices Using Energy Recovery Computing.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018
FinSAL: FinFET-Based Secure Adiabatic Logic for Energy-Efficient and DPA Resistant IoT Devices.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

T-count and Qubit Optimized Quantum Circuit Design of the Non-Restoring Square Root Algorithm.
ACM J. Emerg. Technol. Comput. Syst., 2018

Quantum Circuit Designs of Integer Division Optimizing T-count and T-depth.
CoRR, 2018

Smart Home Environment for Mild Cognitive Impairment Population: Solutions to Improve Care and Quality of Life.
IEEE Consumer Electron. Mag., 2018

Internet of Things-Based Consumer Electronics: Reviewing Existing Consumer Electronic Devices, Systems, and Platforms and Exploring New Research Paradigms.
IEEE Consumer Electron. Mag., 2018

Solar Cell Based Physically Unclonable Function for Cybersecurity in IoT Devices.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Amazon Echo Enabled IoT Home Security System for Smart Home Environment.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

Towards Photoplethysmogram Based Non-Invasive Blood Pressure Classification.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

Hardware Trojan Detection in Implantable Medical Devices Using Adiabatic Computing.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018

Energy-recovery based hardware security primitives for low-power embedded devices.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

Panel theme: Energy and cybersecurity constraints on consumer electronics.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

IoT based indoor location detection system for smart home environment.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

T-count Optimized Quantum Circuits for Bilinear Interpolation.
Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

2017
Automatic synthesis of quaternary quantum circuits.
J. Supercomput., 2017

Efficient Circuit Design of Reversible Square.
Trans. Comput. Sci., 2017

Energy-efficient magnetic 4-2 compressor.
Microelectron. J., 2017

Design exploration of a Symmetric Pass Gate Adiabatic Logic for energy-efficient and secure hardware.
Integr., 2017

T-count Optimized Design of Quantum Integer Multiplication.
CoRR, 2017

Stress Detection and Management: A Survey of Wearable Smart Health Devices.
IEEE Consumer Electron. Mag., 2017

Heuristic Based Majority/Minority Logic Synthesis for Emerging Technologies.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Adiabatic Computing Based Low-Power and DPA-Resistant Lightweight Cryptography for IoT Devices.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Design of Quantum Circuits for Galois Field Squaring and Exponentiation.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Quantum Circuit Designs of Integer Division Optimizing T-Count and T-Depth.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

Security Evaluation of MTJ/CMOS Circuits Against Power Analysis Attacks.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017

Energy-efficient magnetic circuits based on nanoelectronic devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Design of majority logic based approximate arithmetic circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Low-Power and Secure Lightweight Cryptography Via TFET-Based Energy Recovery Circuits.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017

UTB-SOI based adiabatic computing for low-power and secure IoT devices.
Proceedings of the 12th Annual Conference on Cyber and Information Security Research, 2017

2016
Erratum to: Design procedures and NML cost analysis of reversible barrel shifters optimizing garbage and ancilla lines.
J. Supercomput., 2016

Design procedures and NML cost analysis of reversible barrel shifters optimizing garbage and ancilla lines.
J. Supercomput., 2016

Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier.
J. Supercomput., 2016

Mapping of Subtractor and Adder-Subtractor Circuits on Reversible Quantum Gates.
Trans. Comput. Sci., 2016

Design Methodologies for Reversible Logic Based Barrel Shifters.
J. Circuits Syst. Comput., 2016

A Survey of Affective Computing for Stress Detection: Evaluating technologies in stress detection for better health.
IEEE Consumer Electron. Mag., 2016

Design of quaternary 4-2 and 5-2 compressors for nanotechnology.
Comput. Electr. Eng., 2016

Energy-Efficient and Secure S-Box Circuit Using Symmetric Pass Gate Adiabatic Logic.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Exploring Human Body Communications for IoT Enabled Ambulatory Health Monitoring Systems.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

IoT-Based Fall Detection for Smart Home Environments.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

FinSAL: A novel FinFET based Secure Adiabatic Logic for energy-efficient and DPA resistant IoT devices.
Proceedings of the IEEE International Conference on Rebooting Computing, 2016

QUALPUF: A Novel Quasi-Adiabatic Logic based Physical Unclonable Function.
Proceedings of the 11th Annual Cyber and Information Security Research Conference, 2016

2015
Reversible logic based multiplication computing unit using binary tree data structure.
J. Supercomput., 2015

Reversible Logic Based Mapping of Quaternary Sequential Circuits Using QGFSOP Expression.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Design of Testable Adder Circuits for Spintronics Based Nanomagnetic Computing.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

2014
Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits.
Proceedings of the Field-Coupled Nanocomputing - Paradigms, Progress, and Perspectives, 2014

Design of Reversible Adder-Subtractor and its Mapping in Optical Computing Domain.
Trans. Comput. Sci., 2014

Efficient reversible NOR gates and their mapping in optical computing domain.
Microelectron. J., 2014

Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

Design of Dedicated Reversible Quantum Circuitry for Square Computation.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

2013
Design of Testable Reversible Sequential Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder.
Trans. Comput. Sci., 2013

Design of efficient reversible logic-based binary and BCD adder circuits.
ACM J. Emerg. Technol. Comput. Syst., 2013

A new CRL gate as super class of Fredkin gate to design reversible quantum circuits.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2012
Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future.
Proceedings of the 25th International Conference on VLSI Design, 2012

Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Mach-Zehnder interferometer based design of all optical reversible binary adder.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Reversible Logic Based Concurrent Error Detection Methodology For Emerging Nanocircuits
CoRR, 2011

A new reversible design of BCD adder.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs.
ACM J. Emerg. Technol. Comput. Syst., 2010

Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2009
Efficient Reversible Logic Design of BCD Subtractors.
Trans. Comput. Sci., 2009

Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Concurrently Testable FPGA Design for Molecular QCA using Conservative Reversible Logic Gate.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2007
Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2007

Designing Efficient Online Testable Reversible Adders With New Reversible Gate.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Design of Reversible Sequential Elements With Feasibility of Transistor Implementation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Partial Reversible Gates(PRG) for Reversible BCD Arithmetic.
Proceedings of the 2007 International Conference on Computer Design, 2007

2006
Combined Integer and Floating Point Multiplication Architecture(CIFM) for FPGAs and Its Reversible Logic Implementation
CoRR, 2006

Reversible Logic to Cryptographic Hardware: A New Paradigm
CoRR, 2006

Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format
CoRR, 2006

Reversible Programmable Logic Array (RPLA) using Fredkin & Feynman Gates for Industrial Electronics and Applications
CoRR, 2006

VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics
CoRR, 2006

Novel Reversible TSG Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU
CoRR, 2006

An Extension to DNA Based Fredkin Gate Circuits: Design of Reversible Sequential Circuits using Fredkin Gates
CoRR, 2006

A New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits
CoRR, 2006

Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Modified Montgomery Modular Multiplication Using 4: 2 Compressor and CSA Adder.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

Novel and Efficient 4: 2 and 5: 2 Compressors with Minimum Number of Transistors Designed for Low-Power Operations.
Proceedings of the 2006 International Conference on Embedded Systems & Applications, 2006

Design of Novel Reversible Carry Look-Ahead BCD Subtractor.
Proceedings of the 9th International Conference in Information Technology, 2006

A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs.
Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

Novel NAND and AND Gate Using DNA Ligation and Two Transistors Implementations.
Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

A Reversible Programmable Logic Array (RPLA) Using Fredkin and Feynman Gates for Industrial Electronics and Applications.
Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

Modified Carry Look Ahead BCD Adder With CMOS and Reversible Logic Implementation.
Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

Transistor Realization of Reversible TSG Gate and Reversible Adder Architectures.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Novel Reversible Multiplier Architecture Using Reversible TSG Gate.
Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006

Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture.
Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006

The New BCD Subtractor and Its Reversible Logic Implementation.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

2005
Implementation of A Fast Square In RSA Encryption/Decryption Architecture.
Proceedings of The 2005 International Conference on Security and Management, 2005

Faster RSA Encryption/Decryption Architecture Using an Efficient High Speed Overlay Multiplier.
Proceedings of The 2005 International Conference on Security and Management, 2005

Reversible Logic Synthesis of Half, Full and Parallel Subtractors.
Proceedings of The 2005 International Conference on Embedded Systems and Applications, 2005

A Reversible Version of 4 x 4 Bit Array Multiplier With Minimum Gates and Garbage Outputs.
Proceedings of The 2005 International Conference on Embedded Systems and Applications, 2005

A Need of Quantum Computing: Reversible Logic Synthesis of Parallel Binary Adder-Subtractor.
Proceedings of The 2005 International Conference on Embedded Systems and Applications, 2005

VLSI Implementation of O(n*n) Sorting Algorithms And Their Hardware Comparison.
Proceedings of The 2005 International Conference on Scientific Computing, 2005

Verilog Coding Style for Efficient Synthesis In FPGA.
Proceedings of the 2005 International Conference on Computer Design, 2005

Design for A Fast And Low Power 2's Complement Multiplier.
Proceedings of the 2005 International Conference on Computer Design, 2005

Design And Analysis of A VLSI Based High Performance Low Power Parallel Square Architecture.
Proceedings of the 2005 International Conference on Algorithmic Mathematics and Computer Science, 2005

A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2004
A Novel Parallel Multiply and Accumulate (V-MAC) Architecture Based on Ancient Indian Vedic Mathematics.
Proceedings of the International Conference on Embedded Systems and Applications, 2004

A Time-Area-Power Efficient Multiplier and Square Architecture Based on Ancient Indian Vedic Mathematics.
Proceedings of the International Conference on Embedded Systems and Applications, 2004

High Speed Efficient N Bit by N Bit Division Algorithm and Architecture Based on Ancient Indian Vedic Mathematics.
Proceedings of the International Conference on Embedded Systems and Applications, 2004

2003
A High Speed Efficient N x N Bit Multiplier Based on Ancient Indian Vedic Mathematics.
Proceedings of the International Conference on VLSI, 2003


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