Qinfu Yang

According to our database, Qinfu Yang authored at least 7 papers between 2009 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Access-Time Minimization for the IJTAG Network Using Data Broadcast and Hardware Parallelism.

Zhanwei Zhong, Guoliang Li, Qinfu Yang, Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

2018

Broadcast-based minimization of the overall access time for the IEEE 1687 network.

Zhanwei Zhong, Guoliang Li, Qinfu Yang, Jun Qian, Krishnendu Chakrabarty

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Access-Time Minimization in the IEEE 1687 Network Using Broadcast and Hardware Parallelism.

Zhanwei Zhong, Guoliang Li, Qinfu Yang, Krishnendu Chakrabarty

Proceedings of the IEEE International Test Conference, 2018

Industrial Case Studies of SoC Test Scheduling Optimization by Selecting Appropriate EDT Architectures.

Guoliang Li, Henry Zhao, Qinfu Yang, Jun Qian, Yu Huang

Proceedings of the IEEE International Test Conference in Asia, 2018

2015

Hybrid Hierarchical and Modular Tests for SoC Designs.

Guoliang Li, Jun Qian, Qinfu Yang, Yuan Zuo, Rui Li, Yu Huang, Mark Kassab, Janusz Rajski

Proceedings of the 24th IEEE North Atlantic Test Workshop, 2015

2013

Scan Test Data Volume Reduction for SoC Designs in EDT Environment.

Guoliang Li, Jun Qian, Yuan Zuo, Rui Li, Qinfu Yang

Proceedings of the 22nd Asian Test Symposium, 2013

2009

Logic BIST Architecture for System-Level Test and Diagnosis.

Jun Qian, Xingang Wang, Qinfu Yang, Fei Zhuang, Junbo Jia, Xiangfeng Li, Yuan Zuo, Jayanth Mekkoth, Jinsong Liu, Hao-Jan Chao, Shianling Wu, Huafeng Yang, Lizhen Yu, FeiFei Zhao, Laung-Terng Wang

Proceedings of the Eighteentgh Asian Test Symposium, 2009