Hao-Jan Chao

According to our database, Hao-Jan Chao authored at least 9 papers between 2005 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2013

A circular pipeline processing based deterministic parallel test pattern generator.

Kuen-Wei Yeh, Jiun-Lang Huang, Hao-Jan Chao, Laung-Terng Wang

Proceedings of the 2013 IEEE International Test Conference, 2013

2012

Physical-design-friendly hierarchical logic built-in self-test - A case study.

Kelvin Nelson, Jaga Shanmugavadivelu, Jayanth Mekkoth, Venkat Ghanta, Jun Wu, Fei Zhuang, Hao-Jan Chao, Shianling Wu, Jie Rao, Lizhen Yu, Laung-Terng Wang

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2010

Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains.

Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Hiroshi Furukawa, Hao-Jan Chao, Boryau Sheu, Jianghao Guo, Wen-Ben Jone

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains.

Shianling Wu, Laung-Terng Wang, Lizhen Yu, Hiroshi Furukawa, Xiaoqing Wen, Wen-Ben Jone, Nur A. Touba, FeiFei Zhao, Jinsong Liu, Hao-Jan Chao, Fangfang Li, Zhigang Jiang

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009

Turbo1500: Core-Based Design for Test and Diagnosis.

Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li

IEEE Des. Test Comput., 2009

Logic BIST Architecture for System-Level Test and Diagnosis.

Jun Qian, Xingang Wang, Qinfu Yang, Fei Zhuang, Junbo Jia, Xiangfeng Li, Yuan Zuo, Jayanth Mekkoth, Jinsong Liu, Hao-Jan Chao, Shianling Wu, Huafeng Yang, Lizhen Yu, FeiFei Zhao, Laung-Terng Wang

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard.

Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li

Proceedings of the 2008 IEEE International Test Conference, 2008

Practical Challenges in Logic BIST Implementation.

Shianling Wu, Hiroshi Furukawa, Boryau Sheu, Laung-Terng Wang, Hao-Jan Chao, Lizhen Yu, Xiaoqing Wen, Michio Murakami

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2005

At-Speed Logic BIST for IP Cores.

B. Cheon, E. Lee, Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Jin Woo Cho, J. Park, Hao-Jan Chao, Shianling Wu

Proceedings of the 2005 Design, 2005