Laung-Terng Wang

According to our database1, Laung-Terng Wang authored at least 58 papers between 1984 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2008, "For leadership in practical design-for-test of integrated circuits".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding.
IEEE Trans. VLSI Syst., 2017

2016
CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator.
J. Electronic Testing, 2016

2015
SDC-TPG: A Deterministic Zero-Inflation Parallel Test Pattern Generator.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014
On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST.
IEICE Transactions, 2014

GPU-based timing-aware test generation for small delay defects.
Proceedings of the 19th IEEE European Test Symposium, 2014

2013
Testing of Synchronizers in Asynchronous FIFO.
J. Electronic Testing, 2013

LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing.
IEEE Design & Test, 2013

On Guaranteeing Capture Safety in At-Speed Scan Testing with Broadcast-Scan-Based Test Compression.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

A circular pipeline processing based deterministic parallel test pattern generator.
Proceedings of the 2013 IEEE International Test Conference, 2013

On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing.
ACM Trans. Design Autom. Electr. Syst., 2012

Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.
ACM Trans. Design Autom. Electr. Syst., 2012

On pinpoint capture power management in at-speed scan test generation.
Proceedings of the 2012 IEEE International Test Conference, 2012

Physical-design-friendly hierarchical logic built-in self-test - A case study.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011
Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Luncheon Speaker: "Introduction to SoC testing".
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011

A novel scan segmentation design method for avoiding shift timing failure in scan testing.
Proceedings of the 2011 IEEE International Test Conference, 2011

2010
Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme.
IEICE Transactions, 2010

Fault Modeling and Analysis for Resistive Bridging Defects in a Synchronizer.
J. Electronic Testing, 2010

CSER: BISER-based concurrent soft-error resilience.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009
Turbo1500: Core-Based Design for Test and Diagnosis.
IEEE Design & Test of Computers, 2009

Analysis of Resistive Open Defects in a Synchronizer.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Logic BIST Architecture for System-Level Test and Diagnosis.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Analysis of Resistive Bridging Defects in a Synchronizer.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Logic Testing.
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008

Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing.
J. Electronic Testing, 2008

VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG.
IEEE Design & Test of Computers, 2008

Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard.
Proceedings of the 2008 IEEE International Test Conference, 2008

On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Practical Challenges in Logic BIST Implementation.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
A Novel ATPG Method for Capture Power Reduction during Scan Testing.
IEICE Transactions, 2007

At-Speed Logic BIST for IP Cores
CoRR, 2007

A novel scheme to reduce power supply noise for high-quality at-speed scan testing.
Proceedings of the 2007 IEEE International Test Conference, 2007

2006
A New Method for Low-Capture-Power Test Generation for Scan Testing.
IEICE Transactions, 2006

A Per-Test Fault Diagnosis Method Based on the X-Fault Model.
IEICE Transactions, 2006

A New ATPG Method for Efficient Capture Power Reduction During Scan Testing.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing.
Proceedings of the 2006 IEEE International Test Conference, 2006

Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

2005
Efficient Test Set Modification for Capture Power Reduction.
J. Low Power Electronics, 2005

On Low-Capture-Power Test Generation for Scan Testing.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Test compression and logic BIST at your fingertips.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Low-capture-power test generation for scan-based at-speed testing.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

At-Speed Logic BIST Architecture for Multi-Clock Designs.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

At-Speed Logic BIST for IP Cores.
Proceedings of the 2005 Design, 2005

2004
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

On per-test fault diagnosis using the X-fault model.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

1988
Circuits for pseudoexhaustive test pattern generation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1988

Hybrid designs generating maximum-length sequences.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1988

Linear Feedback Shift Register Design Using Cyclic Codes.
IEEE Trans. Computers, 1988

1986
Condensed Linear Feedback Shift Register (LFSR) Testing - A Pseudoexhaustive Test Technique.
IEEE Trans. Computers, 1986

A Hybrid Design of Maximum-Length Sequence Generators.
Proceedings of the Proceedings International Test Conference 1986, 1986

Circuits for Pseudo-Exhaustive Test Pattern Generation.
Proceedings of the Proceedings International Test Conference 1986, 1986

1984
Self-Testing of Embedded RAMs.
Proceedings of the Proceedings International Test Conference 1984, 1984


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