Rajkishore Barik

Orcid: 0000-0003-4779-1391

According to our database1, Rajkishore Barik authored at least 38 papers between 2002 and 2021.

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Bibliography

2021
An Experience with Code-Size Optimization for Production iOS Mobile Applications.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2021

2020
Piranha: reducing feature flag debt at uber.
Proceedings of the ICSE-SEIP 2020: 42nd International Conference on Software Engineering, Software Engineering in Practice, Seoul, South Korea, 27 June, 2020

2019
Optimization of swift protocols.
Proc. ACM Program. Lang., 2019

SWIRL: High-performance many-core CPU code generation for deep neural networks.
Int. J. High Perform. Comput. Appl., 2019

SWIRL++ : Evaluating Performance Models to Guide Code Transformation in Convolutional Neural Networks.
Proceedings of the Languages and Compilers for Parallel Computing, 2019

2018
Accelerating Data Analytics on Integrated GPU Platforms via Runtime Specialization.
Int. J. Parallel Program., 2018

Using Dynamic Compilation to Achieve Ninja Performance for CNN Training on Many-Core Processors.
Proceedings of the Euro-Par 2018: Parallel Processing, 2018

2017
Mozart : Efficient Composition of Library Functions for Heterogeneous Execution.
Proceedings of the Languages and Compilers for Parallel Computing, 2017

2016
Automating wavefront parallelization for sparse matrix computations.
Proceedings of the International Conference for High Performance Computing, 2016

Affinity-aware work-stealing for integrated CPU-GPU processors.
Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2016

Latte: a language, compiler, and runtime for elegant and efficient deep neural networks.
Proceedings of the 37th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2016

A black-box approach to energy-aware scheduling on integrated CPU-GPU systems.
Proceedings of the 2016 International Symposium on Code Generation and Optimization, 2016

Automatic data layout generation and kernel mapping for CPU+GPU architectures.
Proceedings of the 25th International Conference on Compiler Construction, 2016

2014
Native offload of Haskell repa programs to integrated GPUs.
Proceedings of the 3rd ACM SIGPLAN workshop on Functional high-performance computing, 2014

Efficient Mapping of Irregular C++ Applications to Integrated GPUs.
Proceedings of the 12th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2014

Inter-iteration Scalar Replacement Using Array SSA Form.
Proceedings of the Compiler Construction - 23rd International Conference, 2014

ADHA: automatic data layout framework for heterogeneous architectures.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

Adaptive heterogeneous scheduling for integrated GPUs.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013
Improved bitwidth-aware variable packing.
ACM Trans. Archit. Code Optim., 2013

A decoupled non-SSA global register allocation using bipartite liveness graphs.
ACM Trans. Archit. Code Optim., 2013

Compiler-Driven Data Layout Transformation for Heterogeneous Platforms.
Proceedings of the Euro-Par 2013: Parallel Processing Workshops, 2013

Interprocedural strength reduction of critical sections in explicitly-parallel programs.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2011
Communication Optimizations for Distributed-Memory X10 Programs.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

2010
Efficient Selection of Vector Instructions Using Dynamic Programming.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Automatic vector instruction selection for dynamic compilation.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
The habanero multicore software research project.
Proceedings of the Companion to the 24th Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2009

Work-first and help-first scheduling policies for async-finish task parallelism.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Interprocedural Load Elimination for Dynamic Optimization of Parallel Programs.
Proceedings of the PACT 2009, 2009

2008
A Static Characterization of Affinity in a Distributed Program.
Proceedings of the 10th IEEE International Conference on High Performance Computing and Communications, 2008

Static Detection of Place Locality and Elimination of Runtime Checks.
Proceedings of the Programming Languages and Systems, 6th Asian Symposium, 2008

2007
Deadlock-free scheduling of X10 computations with bounded resources.
Proceedings of the SPAA 2007: Proceedings of the 19th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2007

May-happen-in-parallel analysis of X10 programs.
Proceedings of the 12th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2007

Extended Linear Scan: An Alternate Foundation for Global Register Allocation.
Proceedings of the Compiler Construction, 16th International Conference, 2007

2006
Optimal Bitwise Register Allocation Using Integer Linear Programming.
Proceedings of the Languages and Compilers for Parallel Computing, 2006

Enhanced Bitwidth-Aware Register Allocation.
Proceedings of the Compiler Construction, 15th International Conference, 2006

2005
Efficient Computation of May-Happen-in-Parallel Information for Concurrent Java Programs.
Proceedings of the Languages and Compilers for Parallel Computing, 2005

2003
An Efficient Algorithm to Compute Delay Set in SPMD Programs.
Proceedings of the High Performance Computing - HiPC 2003, 10th International Conference, 2003

2002
An overview of the BlueGene/L Supercomputer.
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Proceedings of the 2002 ACM/IEEE conference on Supercomputing, 2002


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