Rakefet Kol

According to our database1, Rakefet Kol authored at least 8 papers between 1996 and 2004.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2004
Asynchronous Design By Conversion: Converting Synchronous Circuits into Asynchronous Ones.
Proceedings of the 2004 Design, 2004

2001
An asynchronous instruction length decoder.
IEEE J. Solid State Circuits, 2001

1999
RAPPID: An Asynchronous Instruction Length Decoder.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

1998
<i>Kin</i>: A High Performance Asynchronous Processor Architecture.
Proceedings of the 12th international conference on Supercomputing, 1998

Adaptive synchronization.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits.
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998

1997
A Double-Latched Asynchronous Pipeline.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996
Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems.
Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '96), 1996


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