Chris J. Myers

According to our database1, Chris J. Myers authored at least 125 papers between 1993 and 2020.

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Bibliography

2020
The first 10 years of the international coordination network for standards in systems and synthetic biology (COMBINE).
J. Integr. Bioinform., 2020

Systems Biology Markup Language (SBML) Level 3 Package: Distributions, Version 1, Release 1.
J. Integr. Bioinform., 2020

Specifications of standards in systems and synthetic biology: status and developments in 2020.
J. Integr. Bioinform., 2020

Synthetic biology open language (SBOL) version 3.0.0.
J. Integr. Bioinform., 2020

Synthetic biology open language visual (SBOL visual) version 2.2.
J. Integr. Bioinform., 2020

Local State Space Analysis to Assist Partial Order Reduction.
CoRR, 2020

2019
Approximation Techniques for Stochastic Analysis of Biological Systems.
Proceedings of the Automated Reasoning for Systems Biology and Medicine, 2019

Toward reproducible disease models using the Systems Biology Markup Language.
Simul., 2019

Design of Asynchronous Genetic Circuits.
Proc. IEEE, 2019

Specifications of Standards in Systems and Synthetic Biology: Status and Developments in 2019.
J. Integr. Bioinform., 2019

Synthetic Biology Open Language Visual (SBOL Visual) Version 2.1.
J. Integr. Bioinform., 2019

Synthetic Biology Open Language (SBOL) Version 2.3.
J. Integr. Bioinform., 2019

The Systems Biology Markup Language (SBML): Language Specification for Level 3 Version 2 Core Release 2.
J. Integr. Bioinform., 2019

Approximation Techniques for Stochastic Analysis of Biological Systems.
CoRR, 2019

Harmonizing semantic annotations for computational models in biology.
Briefings Bioinform., 2019

STAMINA: STochastic Approximate Model-Checker for INfinite-State Analysis.
Proceedings of the Computer Aided Verification - 31st International Conference, 2019

2018
Specifications of Standards in Systems and Synthetic Biology: Status and Developments in 2017.
J. Integr. Bioinform., 2018

The Systems Biology Markup Language (SBML): Language Specification for Level 3 Version 2 Core.
J. Integr. Bioinform., 2018

The Systems Biology Markup Language (SBML): Language Specification for Level 3 Version 1 Core.
J. Integr. Bioinform., 2018

Synthetic Biology Open Language Visual (SBOL Visual) Version 2.0.
J. Integr. Bioinform., 2018

Synthetic Biology Open Language (SBOL) Version 2.2.0.
J. Integr. Bioinform., 2018

2017
A brief history of COMBINE.
Proceedings of the 2017 Winter Simulation Conference, 2017

Advances in Formal Methods for the Design of Analog/Mixed-Signal Systems: Invited.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Toward Community Standards and Software for Whole-Cell Modeling.
IEEE Trans. Biomed. Eng., 2016

An improved fault-tolerant routing algorithm for a Network-on-Chip derived with formal analysis.
Sci. Comput. Program., 2016

Specifications of Standards in Systems and Synthetic Biology: Status and Developments in 2016.
J. Integr. Bioinform., 2016

Synthetic Biology Open Language (SBOL) Version 2.1.0.
J. Integr. Bioinform., 2016

Guest Editors' Introduction Challenges and Opportunities in Analog/Mixed-Signal CAD.
IEEE Des. Test, 2016

Design of Mixed-Signal Systems With Asynchronous Control.
IEEE Des. Test, 2016

2015
Computational Synthetic Biology: Progress and the Road Ahead.
IEEE Trans. Multi Scale Comput. Syst., 2015

Compositional Model Checking of Concurrent Systems.
IEEE Trans. Computers, 2015

SBML Level 3 package: Hierarchical Model Composition, Version 1 Release 3.
J. Integr. Bioinform., 2015

Specifications of Standards in Systems and Synthetic Biology.
J. Integr. Bioinform., 2015

Systems Biology Markup Language (SBML) Level 2 Version 5: Structures and Facilities for Model Definitions.
J. Integr. Bioinform., 2015

Synthetic Biology Open Language (SBOL) Version 2.0.0.
J. Integr. Bioinform., 2015

JSBML 1.0: providing a smorgasbord of options to encode systems biology models.
Bioinform., 2015

Reachability Analysis Using Extremal Rates.
Proceedings of the NASA Formal Methods - 7th International Symposium, 2015

2014
Introduction to the Special Issue on Computational Synthetic Biology.
ACM J. Emerg. Technol. Comput. Syst., 2014

Stochastic Model Checking of Genetic Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2014

Hierarchical stochastic simulation of genetic circuits.
Proceedings of the 2014 Spring Simulation Multiconference, 2014

LEMA: A tool for the formal verification of digitally-intensive analog/mixed-signal circuits.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip.
Proceedings of the Formal Methods for Industrial Critical Systems, 2014

2013
A new assertion property language for analog/mixed-signal circuits.
Proceedings of the 2013 Forum on specification and Design Languages, 2013

Verification of digitally-intensive analog circuits via kernel ridge regression and hybrid reachability analysis.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Design and Test of Genetic Circuits Using ${\tt iBioSim}$iBioSim.
IEEE Des. Test Comput., 2012

A Compositional Minimization Approach for Large Asynchronous Design Verification.
Proceedings of the Model Checking Software - 19th International Workshop, 2012

An Improvement in Partial Order Reduction Using Behavioral Analysis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Poster Abstract: Methods and Tools for Verification of Cyber-Physical Systems.
Proceedings of the 2012 IEEE/ACM Third International Conference on Cyber-Physical Systems, 2012

Modeling and design automation of biological circuits and systems.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Using decision diagrams to compactly represent the state space for explicit model checking.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Utilizing stochastic model checking to analyze genetic circuits.
Proceedings of the 2012 IEEE Symposium on Computational Intelligence in Bioinformatics and Computational Biology, 2012

Formal Verification of Genetic Circuits.
Proceedings of the Computer Aided Verification - 24th International Conference, 2012

2011
Learning Genetic Regulatory Network Connectivity from Time Series Data.
IEEE ACM Trans. Comput. Biol. Bioinform., 2011

Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

A Behavioral Analysis Approach for Efficient Partial Order Reduction.
Proceedings of the 13th IEEE International Symposium on High-Assurance Systems Engineering, 2011

Erlang-delayed stochastic chemical kinetic formalism for efficient analysis of biological systems with non-elementary reaction effects.
Proceedings of the ACM International Conference on Bioinformatics, 2011

2010
Temperature Control of Fimbriation Circuit Switch in Uropathogenic <i>Escherichia coli</i>: Quantitative Analysis via Automated Model Abstraction.
PLoS Comput. Biol., 2010

Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces.
Int. J. Found. Comput. Sci., 2010

iSSA: An incremental stochastic simulation algorithm for genetic circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Automatic abstraction for verification of cyber-physical systems.
Proceedings of the ACM/IEEE 1st International Conference on Cyber-Physical Systems, 2010

State space reductions for scalable verification of asynchronous designs.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

2009
A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation.
IPSJ Trans. Syst. LSI Des. Methodol., 2009

iBioSim: a tool for the analysis and design of genetic circuits.
Bioinform., 2009

A new verification method for embedded systems.
Proceedings of the 27th International Conference on Computer Design, 2009

Genetic design automation.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008
Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Production-Passage-Time Approximation: A New Approximation Method to Accelerate the Simulation Process of Enzymatic Reactions.
J. Comput. Biol., 2008

A Conservative Framework for Safety-Failure Checking.
IEICE Trans. Inf. Syst., 2008

Hazard Checking of Timed Asynchronous Circuits Revisited.
Fundam. Informaticae, 2008

A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper).
Proceedings of the 8th International Conference on Application of Concurrency to System Design (ACSD 2008), 2008

2007
Synthesis of Timed Circuits Based on Decomposition.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Application of Automated Model Generation Techniques to Analog/Mixed-Signal Circuits.
Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007

Bounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver.
Proceedings of the Automated Technology for Verification and Analysis, 2007

Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces.
Proceedings of the Automated Technology for Verification and Analysis, 2007

The Design of a Genetic Muller C-Element.
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007

Symbolic Model Checking of Analog/Mixed-Signal Circuits.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Automated Abstraction Methodology for Genetic Regulatory Networks.
Trans. Comp. Sys. Biology, 2006

Verification of timed circuits with failure-directed abstractions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

The Case for Analog Circuit Verification.
Electron. Notes Theor. Comput. Sci., 2006

Verification of analog/mixed-signal circuits using labeled hybrid petri nets.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Abstracted Stochastic Analysis of Type 1 Pili Expression in E.coli.
Proceedings of the 2006 International Conference on Bioinformatics & Computational Biology, 2006

Effective Contraction of Timed STGs for Decomposition Based Timed Circuit Synthesis.
Proceedings of the Automated Technology for Verification and Analysis, 2006

ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation.
Proceedings of the Sixth International Conference on Computer and Information Technology (CIT 2006), 2006

2005
Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits.
IEICE Trans. Inf. Syst., 2005

Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation.
IEICE Trans. Inf. Syst., 2005

High Level Synthesis of Timed Asynchronous Circuits.
Proceedings of the 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 2005

2004
Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets.
Proceedings of the Automated Technology for Verification and Analysis: Second International Conference, 2004

Synthesis of Speed Independent Circuits Based on Decomposition.
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004

2003
Modular verification of timed circuits using automatic abstraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

2002
Direct synthesis of timed circuits from free-choice STGs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Efficient algorithms for exact two-level hazard-free logic minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Modular Synthesis of Timed Circuits using Partial Order Reduction.
Electron. Notes Theor. Comput. Sci., 2002

Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method.
Proceedings of the 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 2002

Cell library for automatic synthesis of analog error control decoders.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Automatic Derivation of Timing Constraints by Failure Analysis.
Proceedings of the Computer Aided Verification, 14th International Conference, 2002

2001
Timed circuit verification using TEL structures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Analog decoding of product codes.
Proceedings of the 2001 IEEE Information Theory Workshop, 2001

Automatic Abstraction for Verification of Timed Circuits and Systems.
Proceedings of the Computer Aided Verification, 13th International Conference, 2001

Framework of Timed Trace Theoretic Verification Revisited.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Efficient Exact Two-Level Hazard-Free Logic Minimization.
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001

Timed circuits: a new paradigm for high-speed design.
Proceedings of ASP-DAC 2001, 2001

Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOS.
Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 2001

A Standard-Cell Self-Timed Multiplier for Energy and Area Critical Synchronous Systems.
Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 2001

Asynchronous circuit design.
Wiley, ISBN: 978-0-471-41543-5, 2001

2000
Interfacing synchronous and asynchronous modules within a high-speed pipeline.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Timed state space exploration using POSETs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Stochastic cycle period analysis in timed circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Achieving Fast and Exact Hazard-Free Logic Minimization of Extended Burst-Mode gC Finite State Machines.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999
POSET timing and its application to the synthesis and verification of gate-level timed circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Timed Circuit Synthesis Using Implicit Methods.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Architectural Synthesis of Timed Asynchronous Systems.
Proceedings of the IEEE International Conference On Computer Design, 1999

Direct synthesis of timed asynchronous circuits.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

RAPPID: An Asynchronous Instruction Length Decoder.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

Verification of Delayed-Reset Domino Circuits Using ATACS.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

1998
Covering conditions and algorithms for the synthesis of speed-independent circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Verification of Timed Systems Using POSETs.
Proceedings of the Computer Aided Verification, 10th International Conference, 1998

Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits.
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998

1997
An asynchronous implementation of the maxlist algorithm.
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

Efficient Timing Analysis Algorithms for Timed State Space Exploration.
Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '97), 1997

1995
Technology mapping of timed circuits.
Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995

Automatic synthesis of gate-level timed circuits with choice.
Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995

1994
Automatic Verification of Timed Circuits.
Proceedings of the Computer Aided Verification, 6th International Conference, 1994

1993
Synthesis of timed asynchronous circuits.
IEEE Trans. Very Large Scale Integr. Syst., 1993


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