Kenneth S. Stevens

According to our database1, Kenneth S. Stevens authored at least 68 papers between 1986 and 2023.

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Bibliography

2023
Cyclic Timing Path Evaluation Using Commercial Static Timing Analysis Algorithms.
Proceedings of the 28th IEEE International Symposium on Asynchronous Circuits and Systems, 2023

A Novel Asynchronous Network-On-Chip Based on Source Asynchronous Signaling.
Proceedings of the 28th IEEE International Symposium on Asynchronous Circuits and Systems, 2023

2022
Causal Path Identification for Timed and Sequential Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2020
Automatic Timing Closure for Relative Timed Designs.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Learning Based Timing Closure on Relative Timed Design.
Proceedings of the VLSI-SoC: Design Trends, 2020

Reducing Energy Consumption and Decentralizing Computing through Heat Redistribution.
Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020

2019
Low Power SPI Design Based on Relative Timing Techniques.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

A Transmission Line Enabled Deadlock Free Toroidal Network-on-Chip using Asynchronous Handshake Protocols.
Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019

2017
Physical Design Variation in Relative Timed Asynchronous Circuits.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Design of a low power, relative timing based asynchronous MSP430 microprocessor.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Timing Path-Driven Cycle Cutting for Sequential Controllers.
ACM Trans. Design Autom. Electr. Syst., 2016

Path Based Timing Validation for Timed Asynchronous Design.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Design of a multi-style and multi-frequency FPGA.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Reconfigurable circuit for implementation of family of 4-phase latch protocols.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Qualifying Relative Timing Constraints for Asynchronous Circuits.
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

2014
Interfacing Synchronous and Asynchronous Domains for Open Core Protocol.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

An a-FPGA architecture for relative timing based asynchronous designs.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

A Design Space and its Patterns: Modelling 2phase Asynchronous Pipelines.
Proceedings of the HOWARD-60: A Festschrift on the Occasion of Howard Barringer's 60th Birthday, 2014

Modelling Mixed 4phase Pipelines: Structures and Patterns.
Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

2013
Automatic addition of reset in asynchronous sequential control circuits.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Leveraging the geometric properties of on-chip transmission line structures to improve interconnect performance: A case study in 65nm.
Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

A low power UART design based on asynchronous techniques.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Symbolic verification of timed asynchronous hardware protocols.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Relative timing driven multi-synchronous design: enabling order-of-magnitude energy reduction.
Proceedings of the International Symposium on Physical Design, 2013

Design of low energy, high performance synchronous and asynchronous 64-point FFT.
Proceedings of the Design, Automation and Test in Europe, 2013

SAS: Source Asynchronous Signaling Protocol for Asynchronous Handshake Communication Free from Wire Delay Overhead.
Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013

2011
Energy and Performance Models for Synchronous and Asynchronous Communication.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Design of an Energy-Efficient Asynchronous NoC and Its Optimization Tools for Heterogeneous SoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Editorial - Selected papers from the 16th IEEE International Symposium on Asynchronous Circuits and Systems.
IET Comput. Digit. Tech., 2011

Link pipelining strategies for an application-specific asynchronous NoC.
Proceedings of the NOCS 2011, 2011

Synchronous elasticization at a reduced cost: Utilizing the ultra simple fork and controller merging.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010
Design and Verification of Lazy and Hybrid Implementations of the SELF Protocol.
Proceedings of the VLSI-SoC: Forward-Looking Trends in IC and Systems Design, 2010

Synchronous elasticization: Considerations for correct implementation and MiniMIPS case study.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs.
Proceedings of the NOCS 2010, 2010

Bandwidth optimization in asynchronous NoCs by customizing link wire length.
Proceedings of the 28th International Conference on Computer Design, 2010

Control network generator for latency insensitive designs.
Proceedings of the Design, Automation and Test in Europe, 2010

Concurrency Reduction of Untimed Latch Protocols - Theory and Practice.
Proceedings of the 16th IEEE International Symposium on Asynchronous Circuits and Systems, 2010

2009
Radiation Hardening by Design of Asynchronous Logic for Hostile Environments.
IEEE J. Solid State Circuits, 2009

The Future of Formal Methods and GALS Design.
Proceedings of the 4th International Workshop on the Application of Formal Methods for Globally Asynchronous and Locally Synchronous Design, 2009

Power reduction through physical placement of asynchronous routers.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Automatic synthesis of computation interference constraints for relative timing verification.
Proceedings of the 27th International Conference on Computer Design, 2009

Characterization of Asynchronous Templates for Integration into Clocked CAD Flows.
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009

2008
Network Simplicity for Latency Insensitive Cores.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

The Family of 4-phase Latch Protocols.
Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008

2007
Performance Evaluation of Elastic GALS Interfaces and Network Fabric.
Proceedings of the Third International Workshop on Formal Methods for Globally Asynchronous Locally Synchronous Design, 2007

Elastic Flow in an Application Specific Network-on-Chip.
Proceedings of the Third International Workshop on Formal Methods for Globally Asynchronous Locally Synchronous Design, 2007

Guest Editors' Introduction: GALS Design and Validation.
IEEE Des. Test Comput., 2007

Dynamic gates with hysteresis and configurable noise tolerance.
Proceedings of the IFIP VLSI-SoC 2007, 2007

2006
Algorithms for MIS vector generation and pruning.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005
Preface.
Proceedings of the Second Workshop on Globally Asynchronous, Locally Synchronous Design, 2005

Modeling and Verifying Circuits Using Generalized Relative Timing.
Proceedings of the 11th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2005), 2005

2003
Relative timing [asynchronous design].
IEEE Trans. Very Large Scale Integr. Syst., 2003

Energy and Performance Models for Clocked and Asynchronous Communication.
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003

2002
Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Congruent Weak Conformance, a Partial Order among Processes.
Proceedings of the Formal Techniques for Networked and Distributed Systems, 2002

Relative Timing Based Verification of Timed Circuits and Systems.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

2001
An asynchronous instruction length decoder.
IEEE J. Solid State Circuits, 2001

2000
Fsimac: a fault simulator for asynchronous sequential circuits.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

1999
Synthesis of asynchronous control circuits with automatically generated relative timing assumptions.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Multirate as a hardware paradigm.
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

CAD Directions for High Performance Asynchronous Circuits.
Proceedings of the 36th Conference on Design Automation, 1999

Relative Timing.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

RAPPID: An Asynchronous Instruction Length Decoder.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

1998
A Single Chip Low Power Asynchronous Implementation of an FFT Algorithm for Space Applications.
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998

Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits.
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998

1987
The Architecture of FAIM-1.
Computer, 1987

1986
The Post Office-Communication Support for Distributed Ensemble Architectures.
Proceedings of the 6th International Conference on Distributed Computing Systems, 1986


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