Sumit K. Mandal

Orcid: 0000-0002-9294-1603

According to our database¹, Sumit K. Mandal authored at least 32 papers between 2018 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

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Bibliography

2023

ELEMENT: Energy-Efficient Multi-NoP Architecture for IMC-Based 2.5-D Accelerator for DNN Training.

[BibT_eX]

[DOI]

IEEE Des. Test, December, 2023

Fast Analysis Using Finite Queuing Model for Multilayer NoCs.

[BibT_eX]

[DOI]

Shruti Yadav Narayana

IEEE Des. Test, December, 2023

Fast Performance Analysis for NoCs With Weighted Round-Robin Arbitration and Finite Buffers.

[BibT_eX]

[DOI]

Sumit K. Mandal

Shruti Yadav Narayana

IEEE Trans. Very Large Scale Integr. Syst., May, 2023

CANNON: Communication-Aware Sparse Neural Network Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2023

Machine Learning-based Low Overhead Congestion Control Algorithm for Industrial NoCs.

[BibT_eX]

[DOI]

Shruti Yadav Narayana

CoRR, 2023

Achieving Datacenter-scale Performance through Chiplet-based Manycore Architectures.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

A Lightweight Congestion Control Technique for NoCs with Deflection Routing.

[BibT_eX]

[DOI]

Shruti Yadav Narayana

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Benchmarking Heterogeneous Integration with 2.5D/3D Interconnect Modeling.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

SWAP: A Server-Scale Communication-Aware Chiplet-Based Manycore PIM Accelerator.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2022

COIN: Communication-Aware In-Memory Acceleration for Graph Convolutional Networks.

[BibT_eX]

[DOI]

Sumit K. Mandal

Gokul Krishnan

A. Alper Goksoy

Gopikrishnan Ravindran Nair

Yu Cao

Ümit Y. Ogras

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Enabling Software-Defined RF Convergence with a Novel Coarse-Scale Heterogeneous Processor.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Big-Little Chiplets for In-Memory Acceleration of DNNs: A Scalable Heterogeneous Architecture.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2021

Front-End Architecture Design for Low-Complexity 3-D Ultrasound Imaging Based on Synthetic Aperture Sequential Beamforming.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

FLASH: Fast Neural Architecture Search with Hardware Optimization.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2021

SIAM: Chiplet-based Scalable In-Memory Acceleration with Mesh for Deep Neural Networks.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2021

Analytical Performance Modeling of NoCs under Priority Arbitration and Bursty Traffic.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2021

Theoretical Analysis and Evaluation of NoCs with Weighted Round-Robin Arbitration.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

System-Level Benchmarking of Chiplet-based IMC Architectures for Deep Neural Network Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

An Energy-aware Online Learning Framework for Resource Management in Heterogeneous Platforms.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2020

Runtime Task Scheduling Using Imitation Learning for Heterogeneous Many-Core Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Latency-Optimized Reconfigurable NoC for In-Memory Acceleration of DNNs.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2020

A Survey on Energy Management for Mobile and IoT Devices.

[BibT_eX]

[DOI]

IEEE Des. Test, 2020

Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs.

[BibT_eX]

[DOI]

IEEE Des. Test, 2020

Determining Mechanical Stress Testing Parameters for FHE Designs with Low Computational Overhead.

[BibT_eX]

[DOI]

IEEE Des. Test, 2020

Analytical modeling of NoCs for fast simulation and design exploration (invited).

[BibT_eX]

[DOI]

Proceedings of the SLIP '20: System-Level Interconnect, 2020

Performance Analysis of Priority-Aware NoCs with Deflection Routing under Traffic Congestion.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Online Adaptive Learning for Runtime Resource Management of Heterogeneous SoCs.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Dynamic Resource Management of Heterogeneous Mobile Platforms via Imitation Learning.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Analytical Performance Models for NoCs with Multiple Priority Traffic Classes.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2019

A Deep Q-Learning Approach for Dynamic Management of Heterogeneous Processors.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2019

2018

Online learning for adaptive optimization of heterogeneous SoCs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

Sumit K. Mandal

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